Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 485-496

  Yan, Guihai ^a,b   Liang, Xiaoyao ^c   Han, Yinhe ^a,b   Li, Xiaowei ^a  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

^b UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

^c NVIDIA   (United States)

Author keywords

Complimentary effects; Delay sensor; PVT variations; Thread migration; Timing emergency

Indexed keywords

CO-OPTIMIZATION; CORE LEVELS; MULTI-CORE PROCESSOR; MULTIPLE PROGRAM; NANOSCALE TECHNOLOGIES; PERFORMANCE BENEFITS; PRIMARY CIRCUITS; PROCESSING CORE; PVT VARIATIONS; SYSTEM FAIRNESS; THREAD MIGRATION;

COMPUTERS; FOURIER TRANSFORMS; FREQUENCY DOMAIN ANALYSIS; NANOTECHNOLOGY; SENSORS; TIME MEASUREMENT; TIMING CIRCUITS; WAVELET TRANSFORMS;

COMPUTER ARCHITECTURE;

EID: 77954975382     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1816025     Document Type: Conference Paper

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