Tribeca: Design for PVT variations with local recovery and fine-grained adaptation

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 435-446

  Gupta, Meeta S ^a   Rivers, Jude A ^b   Bose, Pradip ^b   Wei, Gu Yeon ^a   Brooks, David ^a  

^a HARVARD UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Availability and serviceability; C.4 performance of systems : reliability; Performance; Reliability

Indexed keywords

AREA OVERHEAD; AVAILABILITY AND SERVICEABILITY; CMOS TECHNOLOGY; DESIGN CHALLENGES; FAIL-SAFE MECHANISM; FREQUENCY-TUNING; PARAMETER VARIATION; PERFORMANCE OF SYSTEMS; POWER-PERFORMANCE EFFICIENCY; PVT VARIATIONS; RECOVERY MECHANISMS; RECOVERY SCHEME; RELIABILITY PERFORMANCE; RUN-TIME VARIATIONS; RUNTIMES; SPATIAL VARIATIONS; SUPPLY VOLTAGE DROOP; TEMPERATURE FLUCTUATION; TIMING MARGIN; TUNING FREQUENCY; VOLTAGE TUNING; WITHIN DIES;

AVAILABILITY; CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; RELIABILITY; TUNING;

MACHINE DESIGN;

EID: 76749155489     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669168     Document Type: Conference Paper

References (34)

1. T. M. Austin. DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. In MICRO 32, 1999.
2. S. Borkar et al. Parameter variations and impact on circuits and microarchitecture. In DAC, June 2003.
3. K. A. Bowman et al. Energy-efficient and metastability-immune timing-error detection and instruction replay-based recovery circuits for dynamic variation tolerance. In ISSCC, 2008.
4. D. Brooks et al. Poweraware microarchitecture: Design and modeling challenges for nextgeneration microprocessors. IEEE Micro, 2000.
5. S. Chatterjee, C. Weaver, and T. Austin. Efficient Checker Processor Design. In MICRO, 2000.
6. K. Constantinides et al. Bulletproof: A defect-tolerant CMP switch architecture. In HPCA, 2006.
7. D. Ernst et al. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. In MICRO, 2003.
8. R. Franch et al. On-chip timing uncertainty measurements on IBM microprocessors. In IEEE International Test Conference, Oct. 2007.
9. B. Greskamp and J. Torrellas. Paceline: Improving single-thread performance in nanoscale CMPs through core overclocking. In PACT, 2007.
10. M. S. Gupta et al. DeCoR: A Delayed Commit and Rollback Mechanism for Handling Inductive Noise in Processors. In HPCA, 2008.
11. V. Gutnik and A. Chandrakasan. On-chip picosecond time measurement. In Symposium on VLSI Circuits, 2000.
12. D. Herell and B. Becker. Modelling of Power Distribution Systems for High-Performance Microprocessors. In IEEE TAP, 1999.
13. International Technology Roadmap for Semiconductors. Process integration, devices and structures, 2007.
14. V. Iyengar, L. Trevillyan, and P. Bose. Representative Traces for Processor Models with Infinite Cache. In HPCA, 1996.
15. R. Joseph et al. Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. In HPCA, 2003.
16. K. Kanda et al. Design impact of positive temperature dependence on drain current in sub- 1-V CMOS VLSIs. JSSC, 36.
17. H. Q. Le et al. IBM POWER6 microarchitecture. IBM Journal of Research and Development, 51(6), 2007.
18. X. Liang et al. ReVIVaL: Variation Tolerant Architecture Using Voltage Interpolation and Variable Latency. In ISCA, 2008.
19. M. Mack, W. Sauer, S. Swaney, and B. Mealy. IBM POWER6 reliability. IBM Journal of Research and Development, 51(6), 2007.
20. A. A. Merchant, D. J. Sagger, and D. D. Boggs. Computer processor with a replay system. United States Patent 6,163,838, Dec. 2000.
21. K. Mistry et al. A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% pb-free packaging. In IEDM, 2007.
22. M. D. Powell and T. N. Vijaykumar. Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. In ISLPED, 2003.
23. V. J. Reddi et al. Voltage Emergency Prediction: A Signature-Based Approach To Reducing Voltage Emergencies. In HPCA, 2009.
24. S. J. Russell and P. Norvig. Artificial Intelligence: A Modern Approach. Prentice Hall, second edition, 2003.
25. S. Sarangi, B. Greskamp, A. Tiwari, and J. Torrellas. EVAL: Utilizing Processors with Variation-Induced Timing Errors. In MICRO, 2008.
26. S. R. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas. VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects. IEEE TSM, February 2008.
27. S. Shyam et al. Ultra Low-Cost Defect Protection for Microprocessor Pipelines. In ASPLOS, 2006.
28. K. Skadron et al. Temperature-aware microarchitecture. In ISCA, 2003.
29. Y. Tamir and M. Tremblay. High-performance fault tolerant vlsi systems using micro rollback. IEEE TOC, 39(4), 1990.
30. R. Teodorescu et al. Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. In MICRO, 2007.
31. J. Tschanz et al. Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging. In ISSCC, 2007.
32. A. Uht. Achieving typical delays in synchronous systems via timing error toleration. Electrical and Computer Engineering Tech Report 032000-0100, University of Rhode Island, March 2000.
33. X. Vera, O. Unsal, and A. Gonzalez. X-Pipe: An Adaptive Resilient Microarchitecture for Parameter Variations. In ASGI, 2006.
34. C. Weaver and T. M. Austin. A Fault Tolerant Approach to Microprocessor Design. In DSN, 2001.