Mitigating parameter variation with dynamic fine-grain body biasing?

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 27-39

  Teodorescu, Radu ^a   Nakano, Jun ^a,b   Tiwari, Abhishek ^a   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b IBM JAPAN LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS VOLTAGE;

BODY BIASING; DYNAMIC CONDITIONS; DYNAMIC VOLTAGE AND FREQUENCY SCALING (DVFS); FIXED FREQUENCIES; INTERNATIONAL SYMPOSIUM; LEAKAGE POWER; LEAKAGE PROPERTIES; MANUFACTURING TIME; MICRO ARCHITECTURES; NORMAL MODES; PARAMETER VARIATIONS; PROCESSOR CHIPS; RE EVALUATION; VOLTAGE BIASING;

AGRICULTURAL PRODUCTS;

EID: 47349093600     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.43     Document Type: Conference Paper

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