1.3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 3, 2006, Pages 220-224

  Staszewski, Robert Bogdan ^a   Vemulapalli, Sudheer ^a   Vallur, Prasant ^a   Wallberg, John ^a   Balsara, Poras T ^b  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

All digital; calibration; compensation; deep submicrometer CMOS; frequency synthesizer; time to digital converter (TDC)

Indexed keywords

DIGITAL CIRCUITS; ELECTRIC INVERTERS; FREQUENCY CONVERTERS; FREQUENCY SYNTHESIZERS; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; PHASE LOCKED LOOPS; TIMING CIRCUITS; TRANSCEIVERS;

ALL-DIGITAL PHASE-LOCKED LOOP; DEEP-SUBMICROMETER; FREQUENCY SYNTHESIS; INVERTER PROPAGATION DELAY; LARGE SYSTEM-ON-CHIP; LOGIC-LEVEL REGENERATIVE TIMING; TIME-TO-DIGITAL CONVERTER (TDC);

CMOS INTEGRATED CIRCUITS;

EID: 33644996419     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2005.858754     Document Type: Article

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