EVAL: Utilizing processors with variation-induced timing errors

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue 2008 PROCEEDINGS, 2008, Pages 423-434

  Sarangi, Smruti ^a   Greskamp, Brian ^a   Tiwari, Abhishek ^a   Torrellas, Josep ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA COST; HIGH-DIMENSIONAL; MACHINE LEARNING ALGORITHMS; MICRO ARCHITECTURES; PARAMETER VALUES; PARAMETER VARIATION; PROCESSOR PERFORMANCE; TIMING ERRORS; TRADE OFF;

EDUCATION; INTEGRATED CIRCUITS; LEARNING ALGORITHMS; TIME MEASUREMENT;

ERRORS;

EID: 66749110356     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2008.4771810     Document Type: Conference Paper

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