90nm 4.7ps-Resolution 0.7-LSB single-shot precision and 19pJ-per-shot local passive interpolation time-to-digital converter with on-chip characterization

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 548-550

  Henzler, Stephan ^a   Koeppe, Siegmar ^a   Kamp, Winfried ^a   Mulatz, Hans ^b   Schmitt Landsiedel, Doris ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR COMPENSATION; INTERPOLATION;

ACTIVE COMPENSATION; CLOCK-JITTER; ON CHIPS; SINGLE SHOTS; TIME TO DIGITAL CONVERTERS;

FREQUENCY CONVERTERS;

EID: 46749143423     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523300     Document Type: Conference Paper

References (7)

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2. P. Dudek, S. Szczepanski, J. Hatfield, "A High-Resolution CMOS Time-to-Digital Converter utilizing a Vernier Delay Line," IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000.
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7. S. Henzler, S. Koeppe, D. Lorenz et. al., "Variation Tolerant High-Resolution and Low Latency Time-to-Digital Converter," ESSCIRC, Sept. 2007.