-
1
-
-
77954206664
-
-
SimpleScalar toolset. < http://www.simplescalar.com >.
-
-
-
-
3
-
-
27544458902
-
Computing architectural vulnerability factors for address-based structures
-
A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S.S. Mukherjee, R. Rangan, Computing architectural vulnerability factors for address-based structures, in: Proceedings of the International Symposium on Computer Architecture, 2005, pp. 532-543.
-
(2005)
Proceedings of the International Symposium on Computer Architecture
, pp. 532-543
-
-
Biswas, A.1
Racunas, P.2
Cheveresan, R.3
Emer, J.4
Mukherjee, S.S.5
Rangan, R.6
-
5
-
-
3042607840
-
SRAM ser in 90, 130 and 180 nm bulk and SOI technologies
-
E.H. Cannon, D.D. Reinhardt, P.S. Makowenskyj, SRAM SER in 90, 130 and 180 nm bulk and SOI technologies, in: Proceedings of the International Reliability Physics Symposium, 2004, pp. 300-304.
-
(2004)
Proceedings of the International Reliability Physics Symposium
, pp. 300-304
-
-
Cannon, E.H.1
Reinhardt, D.D.2
Makowenskyj, P.S.3
-
6
-
-
11044221639
-
Triple module redundancy design techniques for virtex FPGAs
-
V1.0.1
-
C. Carmichael Triple module redundancy design techniques for virtex FPGAs Xilinx Application Notes 197 v1.0.1 2006 1 37
-
(2006)
Xilinx Application Notes
, vol.197
, pp. 1-37
-
-
Carmichael, C.1
-
7
-
-
0012943363
-
Error-correcting Codes for Semiconductor Memory Applications: A State of the Art Review
-
second ed. Digital Press
-
C.L. Chen, and M.Y. Hsiao Error-correcting Codes for Semiconductor Memory Applications: A State of the Art Review second ed. Reliable Computer Systems - Design and Evaluation 1992 Digital Press pp. 771-786
-
(1992)
Reliable Computer Systems - Design and Evaluation
-
-
Chen, C.L.1
Hsiao, M.Y.2
-
8
-
-
31144431627
-
Soft errors issues in low-power caches
-
V. Degalahal, L. Li, V. Narayanan, M. Kandemir, and M.J. Irwin Soft errors issues in low-power caches IEEE Transactions on Very Large Scale Integration Systems 13 10 2005 1157 1166
-
(2005)
IEEE Transactions on Very Large Scale Integration Systems
, vol.13
, Issue.10
, pp. 1157-1166
-
-
Degalahal, V.1
Li, L.2
Narayanan, V.3
Kandemir, M.4
Irwin, M.J.5
-
9
-
-
33846660053
-
Exploiting narrow values for soft error tolerance
-
O. Ergin, O. Unsal, X. Vera, and A. Gonzalez Exploiting narrow values for soft error tolerance IEEE Computer Architecture Letters 5 2 2006 45 48
-
(2006)
IEEE Computer Architecture Letters
, vol.5
, Issue.2
, pp. 45-48
-
-
Ergin, O.1
Unsal, O.2
Vera, X.3
Gonzalez, A.4
-
10
-
-
67649663495
-
Mitigating multi-bit soft errors in L1 caches using last-store prediction
-
B.T. Gold, M. Ferdman, B. Falsafi, K. Mai, Mitigating multi-bit soft errors in L1 caches using last-store prediction, in: Proceedings of the Workshop on Architectural Support for Gigascale Integration, 2007.
-
(2007)
Proceedings of the Workshop on Architectural Support for Gigascale Integration
-
-
Gold, B.T.1
Ferdman, M.2
Falsafi, B.3
Mai, K.4
-
11
-
-
0038346239
-
Transient-fault recovery for chip multiprocessors
-
M. Gomaa, C. Scarbrough, T.N. Vijaykumar, I. Pomeranz, Transient-fault recovery for chip multiprocessors, in: Proceedings of the International Symposium on Computer Architecture, 2003, pp. 98-109.
-
(2003)
Proceedings of the International Symposium on Computer Architecture
, pp. 98-109
-
-
Gomaa, M.1
Scarbrough, C.2
Vijaykumar, T.N.3
Pomeranz, I.4
-
13
-
-
0034789870
-
Impact of CMOS scaling and SOI on soft error rates of logic processes
-
S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walstra, C. Dai, Impact of CMOS scaling and SOI on soft error rates of logic processes, in: Proceedings of the Symposium on VLSI Technology, Digest of Technical Papers, 2001, pp. 73-74.
-
(2001)
Proceedings of the Symposium on VLSI Technology, Digest of Technical Papers
, pp. 73-74
-
-
Hareland, S.1
Maiz, J.2
Alavi, M.3
Mistry, K.4
Walstra, S.5
Dai, C.6
-
14
-
-
0036947936
-
Single-event upset in commercial silicon-on-insulator PowerPC microprocessors
-
F. Irom, F.F. Farmamesh, A.H. Johnson, G.M. Swift, and D.G. Millward Single-event upset in commercial silicon-on-insulator PowerPC microprocessors IEEE Transactions on Nuclear Science 49 6 2002 3148 3155
-
(2002)
IEEE Transactions on Nuclear Science
, vol.49
, Issue.6
, pp. 3148-3155
-
-
Irom, F.1
Farmamesh, F.F.2
Johnson, A.H.3
Swift, G.M.4
Millward, D.G.5
-
16
-
-
0034785079
-
Scaling trends of cosmic rays induced soft errors in static latches beyond 0.18 μm
-
T. Karnik, B. Bloechel, K. Soumyanath, V. De, S. Borkar, Scaling trends of cosmic rays induced soft errors in static latches beyond 0.18 μm, in: Proceedings of Symposium on VLSI Circuits Digest of Technical Papers, 2001, pp. 61-62.
-
(2001)
Proceedings of Symposium on VLSI Circuits Digest of Technical Papers
, pp. 61-62
-
-
Karnik, T.1
Bloechel, B.2
Soumyanath, K.3
De, V.4
Borkar, S.5
-
18
-
-
0034856732
-
Cache decay: Exploiting generational behavior to reduce cache leakage power
-
S. Kaxiras, Z. Hu, M. Martonosi, Cache decay: exploiting generational behavior to reduce cache leakage power, in: Proceedings of the International Symposium on Computer Architecture, 2001, pp. 240-251. (Pubitemid 32825409)
-
(2001)
Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA
, pp. 240-251
-
-
Kaxiras, S.1
Hu, Z.2
Martonosi, M.3
-
20
-
-
47349100793
-
Multi-bit error tolerant caches using two-dimensional error coding
-
J. Kim, N. Hardavellas, K. Mai, B. Falsafi, James Hoe, Multi-bit error tolerant caches using two-dimensional error coding, in: Proceedings of the IEEE/ACM International Symposium on Microarchitecture, 2007, pp. 197-209.
-
(2007)
Proceedings of the IEEE/ACM International Symposium on Microarchitecture
, pp. 197-209
-
-
Kim, J.1
Hardavellas, N.2
Mai, K.3
Falsafi, B.4
Hoe, J.5
-
21
-
-
20344374162
-
Niagara: A 32-way multithreaded Sparc processor
-
P. Kongetira, K. Aingaran, and K. Olukotun Niagara: a 32-way multithreaded Sparc processor IEEE Micro 25 2 2005 21 29
-
(2005)
IEEE Micro
, vol.25
, Issue.2
, pp. 21-29
-
-
Kongetira, P.1
Aingaran, K.2
Olukotun, K.3
-
23
-
-
0034461711
-
Eager writeback - A technique for improving bandwidth utilization
-
H.H.S. Lee, G.S. Tyson, M.K. Farrens, Eager writeback - a technique for improving bandwidth utilization, in: Proceedings of the IEEE/ACM International Symposium on Microarchitecture, 2000, pp. 11-21.
-
(2000)
Proceedings of the IEEE/ACM International Symposium on Microarchitecture
, pp. 11-21
-
-
Lee, H.S.1
Tyson, G.S.2
Farrens, M.K.3
-
24
-
-
16244375550
-
Soft error and energy consumption interactions: A data cache perspective
-
L. Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, Soft error and energy consumption interactions: a data cache perspective, in: Proceedings of the International Symposium on Low Power Electronics and Design, 2004, pp. 132-137.
-
(2004)
Proceedings of the International Symposium on Low Power Electronics and Design
, pp. 132-137
-
-
Li, L.1
Degalahal, V.2
Vijaykrishnan, N.3
Kandemir, M.4
Irwin, M.J.5
-
25
-
-
27544441057
-
SoftArch: An architecture-level tool for modeling and analyzing soft errors
-
X. Li, S.V. Adve, P. Bose, J.A. Rivers, SoftArch: an architecture-level tool for modeling and analyzing soft errors, in: Proceedings of the International Conference on Dependable Systems and Networks, 2005, pp. 496-505.
-
(2005)
Proceedings of the International Conference on Dependable Systems and Networks
, pp. 496-505
-
-
Li, X.1
Adve, S.V.2
Bose, P.3
Rivers, J.A.4
-
26
-
-
84944403418
-
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
-
S.S. Mukherjee, C. Weaver, J. Emer, S.K. Reinhardt, T. Austin, A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, in: Proceedings of the IEEE/ACM International Symposium on Microarchitecture, 2003, pp. 29-42.
-
(2003)
Proceedings of the IEEE/ACM International Symposium on Microarchitecture
, pp. 29-42
-
-
Mukherjee, S.S.1
Weaver, C.2
Emer, J.3
Reinhardt, S.K.4
Austin, T.5
-
27
-
-
28444483117
-
The soft error problem: An architectural perspective
-
S.S. Mukherjee, J. Emer, S.K. Reinhardt, The soft error problem: an architectural perspective, in: Proceedings of the International Symposium on High-performance Computer Architecture, 2005, pp. 243-247.
-
(2005)
Proceedings of the International Symposium on High-performance Computer Architecture
, pp. 243-247
-
-
Mukherjee, S.S.1
Emer, J.2
Reinhardt, S.K.3
-
30
-
-
2442502855
-
SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect
-
K. Osada, K. Yamaguchi, Y. Saitoh, and T. Kawahara SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect IEEE Journal of Solid-State Circuits 39 5 2004 827 833
-
(2004)
IEEE Journal of Solid-State Circuits
, vol.39
, Issue.5
, pp. 827-833
-
-
Osada, K.1
Yamaguchi, K.2
Saitoh, Y.3
Kawahara, T.4
-
31
-
-
0034273728
-
High availability and reliability in the Itanium processor
-
N. Quach High availability and reliability in the Itanium processor IEEE Micro 20 5 2000 61 69
-
(2000)
IEEE Micro
, vol.20
, Issue.5
, pp. 61-69
-
-
Quach, N.1
-
32
-
-
0035691556
-
Dual use of superscalar datapath for transient-fault detection and recovery
-
J. Ray, J. Hoe, B. Falsafi, Dual use of superscalar datapath for transient-fault detection and recovery, in: Proceedings of the IEEE/ACM International Symposium on Microarchitecture, 2001, pp. 214-224.
-
(2001)
Proceedings of the IEEE/ACM International Symposium on Microarchitecture
, pp. 214-224
-
-
Ray, J.1
Hoe, J.2
Falsafi, B.3
-
34
-
-
0035182089
-
Basic block distribution analysis to find periodic behavior and simulation points in applications
-
T. Sherwood, E. Perelman, B. Calder, Basic block distribution analysis to find periodic behavior and simulation points in applications, in: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2001, pp. 3-14.
-
(2001)
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques
, pp. 3-14
-
-
Sherwood, T.1
Perelman, E.2
Calder, B.3
-
35
-
-
0036931372
-
Modeling the effect of technology trends on the soft error rate of combinational logic
-
P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, L. Alvisi, Modeling the effect of technology trends on the soft error rate of combinational logic, in: Proceedings of International Conference on Dependable Systems and Networks, 2002, pp. 389-398.
-
(2002)
Proceedings of International Conference on Dependable Systems and Networks
, pp. 389-398
-
-
Shivakumar, P.1
Kistler, M.2
Keckler, S.W.3
Burger, D.4
Alvisi, L.5
-
36
-
-
29344453384
-
Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations
-
C.W. Slayman Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations IEEE Transactions on Device and Materials Reliability 5 3 2005 397 404
-
(2005)
IEEE Transactions on Device and Materials Reliability
, vol.5
, Issue.3
, pp. 397-404
-
-
Slayman, C.W.1
-
37
-
-
33751547208
-
Reducing data cache susceptibility to soft errors
-
V. Sridharan, H. Asadi, M.B. Tahoori, and D. Kaeli Reducing data cache susceptibility to soft errors IEEE Transactions on Dependable and Secure Computing 3 4 2006 353 364
-
(2006)
IEEE Transactions on Dependable and Secure Computing
, vol.3
, Issue.4
, pp. 353-364
-
-
Sridharan, V.1
Asadi, H.2
Tahoori, M.B.3
Kaeli, D.4
-
38
-
-
0036290674
-
Transient-fault recovery using simultaneous multithreading
-
T.N. Vijaykumar, I. Pomeranz, K. Cheng, Transient-fault recovery using simultaneous multithreading, in: Proceedings of International Symposium on Computer Architecture, 2002, pp. 87-98.
-
(2002)
Proceedings of International Symposium on Computer Architecture
, pp. 87-98
-
-
Vijaykumar, T.N.1
Pomeranz, I.2
Cheng, K.3
-
39
-
-
4544282186
-
Characterizing the effects of transient faults on a high-performance processor pipeline
-
N.J. Wang, J. Quek, T.M. Rafacz, S.J. Patel, Characterizing the effects of transient faults on a high-performance processor pipeline, in: Proceedings of the International Conference on Dependable Systems and Networks, 2004, pp. 61-70.
-
(2004)
Proceedings of the International Conference on Dependable Systems and Networks
, pp. 61-70
-
-
Wang, N.J.1
Quek, J.2
Rafacz, T.M.3
Patel, S.J.4
-
40
-
-
45149093030
-
On the characterization of data cache vulnerability in high-performance embedded microprocessors
-
S. Wang, J. Hu, S.G. Ziavras, On the characterization of data cache vulnerability in high-performance embedded microprocessors, in: Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2006, pp. 14-20.
-
(2006)
Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
, pp. 14-20
-
-
Wang, S.1
Hu, J.2
Ziavras, S.G.3
-
41
-
-
4644320531
-
Techniques to reduce the soft error rate of a high performance microprocessor
-
C. Weaver, J. Emer, S.S. Mukherjee, S.K. Reinhardt, Techniques to reduce the soft error rate of a high performance microprocessor, in: Proceedings of the International Symposium on Computer Architecture, 2004, pp. 264-275.
-
(2004)
Proceedings of the International Symposium on Computer Architecture
, pp. 264-275
-
-
Weaver, C.1
Emer, J.2
Mukherjee, S.S.3
Reinhardt, S.K.4
-
42
-
-
0035722922
-
Simulation of nucleon-induced nuclear reactions in a simplified SRAM structure: Scaling effects on SEU and MBU cross sections
-
F. Wrobel, J.-M. Palau, M.-C. Calvet, O. Bersillon, and H. Duarte Simulation of nucleon-induced nuclear reactions in a simplified SRAM structure: scaling effects on SEU and MBU cross sections IEEE Transactions on Nuclear Science 48 6 2001 1946 1952
-
(2001)
IEEE Transactions on Nuclear Science
, vol.48
, Issue.6
, pp. 1946-1952
-
-
Wrobel, F.1
Palau, J.-M.2
Calvet, M.-C.3
Bersillon, O.4
Duarte, H.5
|