High availability and reliability in the Itanium processor

IEEE Micro

Volumn 20, Issue 5, 2000, Pages 61-69

  Quach, Nhon ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTING CODES (ECC); MACHINE CHECK ABORT (MCA) ARCHITECTURE;

BUFFER STORAGE; CLIENT SERVER COMPUTER SYSTEMS; CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER SYSTEMS PROGRAMMING; DATA REDUCTION; DATA STRUCTURES; ERROR CORRECTION; ERROR DETECTION; RESPONSE TIME (COMPUTER SYSTEMS);

PROGRAM PROCESSORS;

EID: 0034273728     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.877951     Document Type: Article

References (6)

1. Intel IA-64 Architecture Software Developer's Manual, Vol. 1, Intel, Santa Clara, Calif., Order No. 245317-001, Jan. 2000.
2. P. Liden et al., "On Latching Probability of Particle Induced Transients in Combinational Networks," Proc. Symp. Fault Tolerant Computing (FTCS-24), IEEE Press, Piscataway, N.J., 1994, pp. 340-349.
3. Intel IA-64 Architecture Software Developer's Manual, Vol. 2, Intel, Santa Clara, Order No. 245318-001, Jan. 2000.
4. C.L. Chen and M.Y. Hsiao, "Error Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review," IBM J. Research and Development, Vol. 28, No. 2, Mar. 1984.
5. Intel 450NX PCIset Datasheet, Rev. 1.3, Intel, Mar. 1999.
6. IA-64 System Abstract Layer Specification, Intel, Order No. 245359-001, Jan. 2000.