Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2006, Issue , 2006, Pages 215-224

  Kumar, Sumeet ^a   Aggarwal, Aneesh ^a  

^a BINGHAMTON UNIVERSITY   (United States)

Author keywords

Concurrent Error Detection; Reducing Redundancy; Redundant Multi threading; Register File

Indexed keywords

CLOCK SPEED; CONCURRENT ERROR DETECTION; REDUNDANT MULTI-THREADING (RMT); REGISTER FILE;

BINARY CODES; BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; ERROR DETECTION; PROGRAM PROCESSORS; REDUNDANCY; SHIFT REGISTERS;

MICROPROCESSOR CHIPS;

EID: 33748875821     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2006.1598130     Document Type: Conference Paper

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