-
2
-
-
34548119936
-
-
SPEC
-
SPEC 2000 Benchmark. http://www.spec.org
-
(2000)
Benchmark
-
-
-
5
-
-
11044221639
-
Triple module redundancy design techniques for virtex FPGAs
-
Nov
-
C. Carmichael. Triple module redundancy design techniques for virtex FPGAs. Xilinx Aplication Notes 197, v1.0, Nov. 2001.
-
(2001)
Xilinx Aplication Notes
, vol.197
-
-
Carmichael, C.1
-
6
-
-
0012943363
-
Error-correcting codes for semiconductor memory applications: A state of the art review
-
Digital Press, 2nd Ed, pp
-
C. L. Chen and M. Y. Hsiao. Error-correcting codes for semiconductor memory applications: a state of the art review. Reliable Computer Systems - Design and Evaluation, Digital Press, 2nd Ed., pp. 771-786, 1992.
-
(1992)
Reliable Computer Systems - Design and Evaluation
, pp. 771-786
-
-
Chen, C.L.1
Hsiao, M.Y.2
-
8
-
-
31144431627
-
Soft errors issues in low-power caches
-
Oct
-
V. Degalahal, L. Li, V. Narayanan, M. Kandemir, and M. J. Irwin. Soft errors issues in low-power caches. IEEE Trans. on Very Large Scale Integ. Sys., 13(10):1157-1166, Oct. 2005.
-
(2005)
IEEE Trans. on Very Large Scale Integ. Sys
, vol.13
, Issue.10
, pp. 1157-1166
-
-
Degalahal, V.1
Li, L.2
Narayanan, V.3
Kandemir, M.4
Irwin, M.J.5
-
11
-
-
0034789870
-
-
processes. VLSI Technology Digest of Technical Papers, 2001
-
S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walstra, and C. Dai. Impact of CMOS scaling and SOI on soft error rates of logic processes. VLSI Technology Digest of Technical Papers, 2001.
-
Impact of CMOS scaling and SOI on soft error rates of logic
-
-
Hareland, S.1
Maiz, J.2
Alavi, M.3
Mistry, K.4
Walstra, S.5
Dai, C.6
-
12
-
-
0036947936
-
Single-event upset in commercial silicon-on-insulator PowerPC microprocessors
-
Dec
-
F. Irom, F. F. Farmamesh, A. H. Johnson, G. M. Swift, and D. G. Millward. Single-event upset in commercial silicon-on-insulator PowerPC microprocessors. IEEE Trans, on Nucl. Svi., 49(6), Dec. 2002.
-
(2002)
IEEE Trans, on Nucl. Svi
, vol.49
, Issue.6
-
-
Irom, F.1
Farmamesh, F.F.2
Johnson, A.H.3
Swift, G.M.4
Millward, D.G.5
-
13
-
-
0034785079
-
Scaling trends of cosmic rays induced soft errors in static latches beyond 0.18μ
-
T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar. Scaling trends of cosmic rays induced soft errors in static latches beyond 0.18μ. Symp. on VLSI Circuits Digest of Technical Papers, 2001.
-
(2001)
Symp. on VLSI Circuits Digest of Technical Papers
-
-
Karnik, T.1
Bloechel, B.2
Soumyanath, K.3
De, V.4
Borkar, S.5
-
14
-
-
9144234352
-
Characterization of soft errors caused by single event upsets in CMOS processes
-
June
-
T. Karnik, P. Hazucha, and J. Patel. Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans. on Dep. and Sec. Comp, 1(2):128-143, June 2004.
-
(2004)
IEEE Trans. on Dep. and Sec. Comp
, vol.1
, Issue.2
, pp. 128-143
-
-
Karnik, T.1
Hazucha, P.2
Patel, J.3
-
15
-
-
0034856732
-
Cache decay: Exploiting generational behavior to reduce cache leakage power
-
S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: exploiting generational behavior to reduce cache leakage power. Int. Symp. on Comp. Arch., 2001.
-
(2001)
Int. Symp. on Comp. Arch
-
-
Kaxiras, S.1
Hu, Z.2
Martonosi, M.3
-
16
-
-
0036926873
-
Soft error sensitivity characterization for microprocessor dependability enhancement strategy
-
S. Kim and A. K. Somani. Soft error sensitivity characterization for microprocessor dependability enhancement strategy. Int. Conf. on Dep. Sys. and Net., 2002.
-
(2002)
Int. Conf. on Dep. Sys. and Net
-
-
Kim, S.1
Somani, A.K.2
-
17
-
-
33748875821
-
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
-
S. Kumar and A. Aggarwal. Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors. Int. Symp. on High-Per. Comp. Arch., 2006.
-
(2006)
Int. Symp. on High-Per. Comp. Arch
-
-
Kumar, S.1
Aggarwal, A.2
-
20
-
-
84944403418
-
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
-
Dec
-
S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. Int. Symp. on Micro., Dec. 2003.
-
(2003)
Int. Symp. on Micro
-
-
Mukherjee, S.S.1
Weaver, C.2
Emer, J.3
Reinhardt, S.K.4
Austin, T.5
-
24
-
-
0035691556
-
Dual use of superscalar datapath for transient-fault detection and recovery
-
J. Ray, J. Hoe, and B. Falsafi. Dual use of superscalar datapath for transient-fault detection and recovery. Int. Symp. on Micro., 2001.
-
(2001)
Int. Symp. on Micro
-
-
Ray, J.1
Hoe, J.2
Falsafi, B.3
-
26
-
-
0036931372
-
Modeling the effect of technology trends on the soft error rate of combinational logic
-
June
-
P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi. Modeling the effect of technology trends on the soft error rate of combinational logic. Int. Conf. on Dep. Sys. and Net., June 2002.
-
(2002)
Int. Conf. on Dep. Sys. and Net
-
-
Shivakumar, P.1
Kistler, M.2
Keckler, S.W.3
Burger, D.4
Alvisi, L.5
-
27
-
-
33751547208
-
Reducing data cache susceptibility to soft errors
-
V. Sridharan, H. Asadi, M. B. Tahoori, and D. Kaeli. Reducing data cache susceptibility to soft errors. IEEE Trans, on Dep. and Sec. Comp., 3(4): 353-364, 2006.
-
(2006)
IEEE Trans, on Dep. and Sec. Comp
, vol.3
, Issue.4
, pp. 353-364
-
-
Sridharan, V.1
Asadi, H.2
Tahoori, M.B.3
Kaeli, D.4
-
29
-
-
12344256113
-
Modeling the effect of transient errors on high performance microprocessors
-
March
-
N. Wang and S. Patel. Modeling the effect of transient errors on high performance microprocessors. Center for Circuits, Systems, and Software, March 2003.
-
(2003)
Center for Circuits, Systems, and Software
-
-
Wang, N.1
Patel, S.2
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