On the characterization of data cache vulnerability in high-performance embedded microprocessors

Proceedings - 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2006

Volumn , Issue , 2006, Pages 14-20

  Wang, Shuai ^a   Hu, Jie ^a   Ziavras, Sotirios G ^a  

^a NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; ERROR CORRECTION; INTEGRATED CIRCUITS; RADIATION HARDENING; STATIC RANDOM ACCESS STORAGE;

CONVENTIONAL PROTECTION SCHEMES; EMBEDDED MICROPROCESSORS; ENERGETIC PARTICLES; ERROR CORRECTING CODE; PROBABILITY OF ERRORS; RELIABLE MICROPROCESSORS; VULNERABILITY ANALYSIS; WRITE-BACK STRATEGIES;

EMBEDDED SYSTEMS;

EID: 45149093030     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSAMOS.2006.300803     Document Type: Conference Paper

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