Exploiting narrow values for soft error tolerance

IEEE Computer Architecture Letters

Volumn 5, Issue 2, 2006, Pages

  Ergin, Oguz ^a   Unsal, Osman ^b   Vera, Xavier ^c   González, Antonio ^c  

^a TOBB UNIVERSITY OF ECONOMICS AND TECHNOLOGY   (Turkey)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

^c INTEL CORPORATION   (United States)

Author keywords

Data cache; Error correction; Narrow values; Soft errors

Indexed keywords

BIT ERROR RATE; CACHE MEMORY; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; DATA PROCESSING; MICROPROCESSOR CHIPS;

DATA CACHE; NARROW VALUES; SOFT ERRORS; TRANSIENT ERRORS;

ERROR CORRECTION;

EID: 33846660053     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2006.12     Document Type: Article

References (13)

1. Baumann, R., "Soft Errors in Advanced Computer Systems", in IEEE Design & Test of Computers, 2005
2. Brooks, D., and Martonosi, M., "Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance", in HPCA, 1999
3. Canal R., et al., "Very Low Power Pipelines using Significance Compression", in MICRO, 2000
4. Ergin, O., et al., "Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure", in MICRO, 2004
5. Gonzalez, R., et al. "A Content Aware Register File Organization", in ISCA, 2004
6. Hinton, G., et al., "The Microarchitecture of the Pentium 4 Processor", Intel Technology Journal, Q1, 2001
7. Hu, J., et al., "In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability", in DSN 2006
8. Memik, G, et al., "Increasing Register File Immunity to Transient Errors", in DATE'05, 2005
9. Mukherjee, S. S., et al., "A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor", in MICRO, 2003
10. Phelan, R., "Addressing Soft Errors in ARM Core-based Designs", White Paper, ARM, December 2003
11. Semiconductors Industry Association (SIA), International Technology Roadmap for Semiconductors 2003, http://public.itrs.net/Files/2003ITRS/ Home2003.htm.
12. Vijaykumar, T. N., et al., "Transient-Fault Recovery Using Simultaneous Multithreading", in ISCA, 2002
13. Villa, L., et al., "Dynamic Zero Compression for Cache Energy Reduction", in MICRO, 2000