An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2010, Pages

  Woo, Dong Hyuk ^a   Seong, Nak Hee ^a   Lewis, Dean L ^a   Lee, Hsien Hsin S ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CACHE MEMORY; DATA TRANSFER; DYNAMIC RANDOM ACCESS STORAGE; ECONOMIC AND SOCIAL EFFECTS; ELECTRONICS PACKAGING; ENERGY UTILIZATION; MEMORY ARCHITECTURE; MULTICORE PROGRAMMING; NETWORK ARCHITECTURE; PROGRAM PROCESSORS; SUPERCOMPUTERS; SYSTEM BUSES;

3D-STACKED MEMORY; DESIGN TRADEOFF; HIGH FREQUENCY HF; MEMORY BANDWIDTHS; MEMORY HIERARCHY; PERFORMANCE BOTTLENECKS; THROUGH SILICON VIAS; VERY LARGE DATUM;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 77952554764     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/hpca.2010.5416628     Document Type: Conference Paper

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