Rigel: An architecture and scalable programming interface for a 1000-core accelerator

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 140-151

  Kelm, John H ^a   Johnson, Daniel R ^a   Johnson, Matthew R ^a   Crago, Neal C ^a   Tuohy, William ^a   Mahesri, Aqeel ^a   Lumetta, Steven S ^a   Frank, Matthew I ^a   Patel, Sanjay J ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Accelerator; Computer architecture; Low level programming interface

Indexed keywords

A-DENSITY; ACCELERATOR ARCHITECTURES; ADDRESS SPACE; BARRIER OPERATIONS; DESIGN ANALYSIS; DOMAIN SPECIFIC; EXECUTION MODEL; EXPERIMENTAL ANALYSIS; HARDWARE SUPPORTS; INITIAL DESIGN; LOAD-BALANCING; PARALLEL COMPUTATION; POWER EFFICIENCY; PROGRAMMING INTERFACE; PROGRAMMING MODELS; SCALABILITY ISSUE; SOFTWARE TECHNIQUES; SPECIALIZED HARDWARE; TASK DISTRIBUTION; WORK DISTRIBUTION;

ACCELERATION; COMPUTER HARDWARE; COMPUTER PROGRAMMING; HARDWARE; INTERFACES (COMPUTER); PROGRAM PROCESSORS;

COMPUTER ARCHITECTURE;

EID: 70450237431     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555774     Document Type: Conference Paper

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