Microarchitecture soft error vulnerability characterization and mitigation under 3d integration technology

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue 2008 PROCEEDINGS, 2008, Pages 435-446

  Zhang, Wangyuan ^a   Li, Tao ^a  

^a University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D DIE STACKING; 3D TECHNOLOGY; CHIP INTEGRATION; CMOS TECHNOLOGY; ERROR RESILIENCE; HIGH-PERFORMANCE MICROPROCESSORS; IN-FLIGHT INSTRUCTIONS; INTER-LAYERS; MANUFACTURING COST; MICRO ARCHITECTURES; ON CHIPS; ON-CHIP TEMPERATURE; PHYSICAL MECHANISM; PROCESS TECHNOLOGIES; PROGRAM VALUE; REDUCING POWER; REGISTER FILES; RELIABILITY BENEFITS; SCALE DOWN; SEMICONDUCTOR PROCESSING TECHNIQUES; SILICON ON INSULATOR; SOFT ERROR; SOFT ERROR RATE; STACKED STRUCTURE; TRANSIENT FAULTS; VERTICAL STACKING; WIRE DELAYS;

ERROR CORRECTION; FAULT TREE ANALYSIS; MICROPROCESSOR CHIPS; MODELS; RELIABILITY; TECHNOLOGY;

THREE DIMENSIONAL;

EID: 66749142911     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2008.4771811     Document Type: Conference Paper

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