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1
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0242636496
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"A 5.6 Random Cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM Interface"
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H. Pilo, A. Darren, J. Barth, S. Burns, P. Corson, J. Covino, R. Houghton, and S. Lamphier, "A 5.6 Random Cycle 144 Mb DRAM with 1.4 Gb/ s/pin and DDR3-SRAM Interface," IEEE J. Solid-State Circuits 38, 1974 (2003).
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IEEE J. Solid-State Circuits
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Pilo, H.1
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2
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85039467750
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"Hybrid Memory with On Chip Associative Page Addressing, Page Replacement and Control"
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DRAM (or SRAM cache) with translation directory and on-chip control
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R. Matick, "Hybrid Memory with On Chip Associative Page Addressing, Page Replacement and Control," U.S. Patent 4,084,230, 1978; DRAM (or SRAM cache) with translation directory and on-chip control.
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U.S. Patent 4,084,230
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Matick, R.1
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3
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"All Points Addressable Raster Display Memory"
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R. Matick, D. T. Ling, S. Gupta, and F. Dill, "All Points Addressable Raster Display Memory," IBM J. Res. & Dev. 28, 379 (1984).
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85039481711
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"Random Access Memory Having a Second Input/Output Port"
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DRAM with added logic and buffers to speed up graphics (video RAM)
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F. Dill, D. Ling, and R. Matick, "Random Access Memory Having a Second Input/Output Port," U.S. Patent 4,541,075, 1985; DRAM with added logic and buffers to speed up graphics (video RAM).
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U.S. Patent 4,541,075
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Dill, F.1
Ling, D.2
Matick, R.3
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5
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85039471810
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"Distributed, On-Chip Cache"
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included a small, fast SRAM on a memory chip as a cache, and was a precursor to and first version of current ESDRAM (enhanced synchronous DRAM) chips
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R. Matick and D. T. Ling, "Distributed, On-Chip Cache," U.S. Patent 4,577,293, 1986; included a small, fast SRAM on a memory chip as a cache, and was a precursor to and first version of current ESDRAM (enhanced synchronous DRAM) chips.
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U.S. Patent 4,577,293
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Matick, R.1
Ling, D.T.2
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"An Experimental 1 Mbit Cache DRAM with ECC"
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M. Asakura, Y. Matsuda, H. Hidaka, Y. Tanaka, and K. Fujishima, "An Experimental 1 Mbit Cache DRAM with ECC," IEEE J. Solid-State Circuits 25, 5 (1990).
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IEEE J. Solid-State Circuits
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Asakura, M.1
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Proceedings of the 39th Conference on Design Automation (ASM, IEEE), New Orleans, June 10-14
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Pogge, B.1
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85039479458
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"Clock Skew Minimization and Method for Integrated Circuits"
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substrates connected together, face to face, using flip-chip technology
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F. Bozso and P. Emma, "Clock Skew Minimization and Method for Integrated Circuits," U.S. Patent 6,040,203, 2000; substrates connected together, face to face, using flip-chip technology.
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U.S. Patent 6,040,203
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Emma, F.1
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13844267942
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John Wiley & Sons, Inc., New York, multiple device memory cells
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E. R. Hnatek, A User's Handbook of Semiconductor Memories, John Wiley & Sons, Inc., New York, 1977, p. 360; multiple device memory cells.
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Hnatek, E.R.1
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10
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85039485713
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"A 4-Device CMOS Static RAM Cell Using Sub-Threshold Conduction"
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presented at the IEEE Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, 1987; Research Report RC-13171, IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598
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S. E. Schuster, L. M. Terman, and R. L. Franch, "A 4-Device CMOS Static RAM Cell Using Sub-Threshold Conduction," presented at the IEEE Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, 1987; Research Report RC-13171, IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598, 1987.
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Schuster, S.E.1
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Franch, R.L.3
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11
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"A 2 ns Cycle, 3.8 ns Access 512 kb CMOS ECL SRAM with a Fully Pipelined Architecture"
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T. Chappell, B. Chappell, S. Schuster, J. Allen, S. Klepner, R. Joshi, and R. Franch, "A 2 ns Cycle, 3.8 ns Access 512 kb CMOS ECL SRAM with a Fully Pipelined Architecture," IEEE J. Solid-State Circuits 26 1577 (1991).
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IEEE J. Solid-State Circuits
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Chappell, T.1
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"The Evolution of DRAM Cell Technology"
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El-Kareh, B.1
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13
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"A 20ns 64K (4K × 16) NMOS RAM"
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S. E. Schuster, B. Chappell, V. DiLonardo, and P. E. Britton, "A 20ns 64K (4K × 16) NMOS RAM," IEEE J. Solid-State Circuits SC-19 564 (1984).
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IEEE J. Solid-State Circuits
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Schuster, S.E.1
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"Architecture Implications in the Design of Microprocessors"
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IBM Syst. J.
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IBM Syst. J.
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Matick, R.E.1
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"Functional Cache Chip for Improved System Performance"
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R. E. Matick, "Functional Cache Chip for Improved System Performance," IBM J. Res. & Dev. 33, 15 (1989).
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IBM J. Res. & Dev.
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Matick, R.E.1
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18
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0024737820
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"Architecture, Design, and Operating Characteristics of a 12-ns CMOS Functional Cache Chip"
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R. Matick, R. Mao, and S. Ray, "Architecture, Design, and Operating Characteristics of a 12-ns CMOS Functional Cache Chip," IBM J. Res. & Dev. 33, 524 (1989).
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IBM J. Res. & Dev.
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Matick, R.1
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19
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85039483661
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"IBM Embeds DRAM in 0.18-Micron ASICs"
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February 22, Web-published at
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D. Lamers, "IBM Embeds DRAM in 0.18-Micron ASICs," Electronic Engineering Times, February 22, 1999; Web-published at http://www.eetimes.com/showArticle.jhtml?articleID=18300993.
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Electronic Engineering Times
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Lamers, D.1
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85039477818
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"IBM Pushes eDRAM as SRAM Replacement"
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February 13, Web-published at
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S. Deffree, "IBM Pushes eDRAM as SRAM Replacement," Electronic News February 13, 2003; Web-published at http://www.reed-electronics.com/electronicnews/article/ CA276970?text=deffree http://www.reed-electronics.com/electronicnews/article/ CA276970?text=deffree
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Electronic News
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Deffree, S.1
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21
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85039478771
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"IBM Makes Another Run at Embedded DRAM"
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February 13, Web-published at, 144-Mb, 5.6-ns eDRAM to replace SRAM
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M. Clendenin, "IBM Makes Another Run at Embedded DRAM," Electronic Engineering Times, February 13, 2003; Web-published at http://www.eetimes.com/showArticle.jhtml?articleID=18308029; 144-Mb, 5.6-ns eDRAM to replace SRAM.
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Electronic Engineering Times
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"IBM Pushes Embedded DRAM as NEC Changes Tack"
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A. Cataldo, "IBM Pushes Embedded DRAM as NEC Changes Tack," Electronic Engineering Times, February 15, 2003; Web-published at http://www.eetimes.com/showArticle.jhtml?articleID=18303603.
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Electronic Engineering Times
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0035717575
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"A 0.13 μm Logic-Based Embedded DRAM Technology with Electrical Fuses, Cu Interconnect in SiLK™, Sub-7ns Random Access Time and Its Extension to the 0.10/μm Generation"
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V. Klee, J. Norum, R. Weaver, S. S. K. Iyer, C. R. Kothandaraman, J. Chiou, M. Chen, N. Kusaba, S. Lasserre, C. Liang, J. Liu, A. Lu, P. R. Parries, B. J. Park, J. Rice, N. Robson, D. Shum, B. Khan, Y. Liu, A. Sierkowski, C. Waskiewiscz, P. Wensley, T. Wu, J. Yan, and S. S. Iyer, "A 0.13 μm Logic-Based Embedded DRAM Technology with Electrical Fuses, Cu Interconnect in SiLK™, Sub-7ns Random Access Time and Its Extension to the 0.10/μm Generation," Technical Digest, IEEE International Electron Devices Meeting, 2001, p. 407.
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Technical Digest, IEEE International Electron Devices Meeting
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Klee, V.1
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Park, B.J.14
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more..
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J. Barth, D. Anand, J. Dreibelbis, and E. Nelson, "A 300 MHz Multi-Banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2002, p. 156.
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Digest of Technical Papers, IEEE International Solid-State Circuits Conference
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Y. Agata, K. Motomochi, Y. Yoshifumi, M. Shirahama, M. Kurumada, M. Kuroda, H. Sadakata, K. Hayashi, T. Yamada, K. Takahashi, and T. Fujita, "Ah 8ns Random Cycle Embedded RAM Macro with Dual-Port Interleaved DRAM Architecture (D2RAM)," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2002, p. 392.
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Digest of Technical Papers, IEEE Symposium on VLSI Circuits
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Tomashot, S.9
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Addison-Wesley Publishing Co., Inc., Boston
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85039478205
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"Riesling 2K bit, 6 Device SRAM"
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IBM Engineering Specification No. 5123326, September 19, a ∼4-μm technology chip that was used in main memory for the IBM System/360-158, 168, etc. high-end computers
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"Riesling 2K bit, 6 Device SRAM," IBM Engineering Specification No. 5123326, September 19, 1974; a ∼4-μm technology chip that was used in main memory for the IBM System/360-158, 168, etc. high-end computers.
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(1974)
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30
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69949122672
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"Field Effect Transistor Memory"
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filed July 14
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R. H. Dennard, "Field Effect Transistor Memory," U.S. Patent 3,387,286, filed July 14, 1967.
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U.S. Patent 3,387,286
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"A 50 ns 16 Mb DRAM with a 10 ns Data Rate and On-Chip ECC"
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85039468975
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IBM RISC System/6000 Technology; Publication SA23-2619. The cache described on p. 12 of "RISC System/6000 Hardware Overview" and on p. 44 of "Data Cache and Storage Control Units" is based on the cache described in Reference 14 of this paper
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IBM RISC System/6000 Technology; Publication SA23-2619. The cache described on p. 12 of "RISC System/6000 Hardware Overview" and on p. 44 of "Data Cache and Storage Control Units" is based on the cache described in Reference 14 of this paper.
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37
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11144287593
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"An Overview of the BlueGene/L Supercomputer"
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IBM Blue Gene/L Team (IBM and Lawrence Livermore National Laboratory), see also a forthcoming issue of this journal (2005)
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IBM Blue Gene/L Team (IBM and Lawrence Livermore National Laboratory), "An Overview of the BlueGene/L Supercomputer," Proceedings of the 2002 ACM/IEEE Conference on Supercomputing, 2002, p. 1; see also a forthcoming issue of this journal (2005).
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Honolulu, HI, June
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|