Shoestring: Probabilistic soft error reliability on the cheap

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2010, Pages 385-396

  Feng, Shuguang ^a   Gupta, Shantanu ^a   Ansari, Amin ^a   Mahlke, Scott ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Compiler analysis; Error detection; Fault injection

Indexed keywords

COMMODITY PROCESSORS; COMPILE TIME; COMPILER ANALYSIS; CRITICAL DOMAIN; DEVICE RELIABILITY; FAILURE RATE; FAULT INJECTION; HIGH-RELIABILITY; INTELLIGENT ANALYSIS; MINIMALLY INVASIVE; PROFIT MARGIN; PROGRAM CODE; RELIABILITY IMPROVEMENT; RELIABLE OPERATION; SOFT ERROR; TECHNOLOGY SCALING;

BUDGET CONTROL; COMPUTER OPERATING SYSTEMS; COST BENEFIT ANALYSIS; ERROR CORRECTION; FAULT DETECTION; LINGUISTICS; MICROPROCESSOR CHIPS; PROFITABILITY; PROGRAM COMPILERS; QUALITY ASSURANCE; QUERY LANGUAGES; SOFTWARE RELIABILITY;

ERROR DETECTION;

EID: 77952275692     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1736020.1736063     Document Type: Conference Paper

References (42)

1. T. Austin. Diva: a reliable substrate for deep submicron microarchitecture design. In Proc. of the 32nd Annual International Symposium on Microarchitecture, pages 196-207, 1999. (Pubitemid 30516605)
2. W. Bartlett and L. Spainhower. Commercial fault tolerance: A tale of two systems. IEEE Transactions on Dependable and Secure Computing, 1(1):87-96, 2004. (Pubitemid 40134580)
3. D. Bernick, B. Bruckert, P. D. Vigna, D. Garcia, R. Jardine, J. Klecka, and J. Smullen. Nonstop advanced architecture. In International Conference on Dependable Systems and Networks, pages 12-21, June 2005.
4. J. A. Blome, S. Gupta, S. Feng, S. Mahlke, and D. Bradley. Cost-efficient soft error protection for embedded microprocessors. In Proc. of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 421-431, 2006. (Pubitemid 47113129)
5. S. Borkar. Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro, 25(6):10-16, 2005.
6. F. A. Bower, D. J. Sorin, and S. Ozev. A mechanism for online diagnosis of hard faults in microprocessors. In Proc. of the 38th Annual International Symposium on Microarchitecture, pages 197-208, 2005.
7. M. Gomaa and T. Vijaykumar. Opportunistic transient-fault detection. In Proc. of the 32nd Annual International Symposium on Computer Architecture, pages 172-183, June 2005.
8. M. A. Gomaa, C. Scarbrough, I. Pomeranz, and T. N. Vijaykumar. Transient-fault recovery for chip multiprocessors. In Proc. of the 30th Annual International Symposium on Computer Architecture, pages 98-109, 2003.
9. J. Kim, N. Hardavellas, K. Mai, B. Falsafi, and J. C. Hoe. Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. In Proc. of the 40th Annual International Symposium on Microarchitecture, 2007.
10. C. Lattner and V. Adve. LLVM: A compilation framework for life-long program analysis & transformation. In Proc. of the 2004 International Symposium on Code Generation and Optimization, pages 75-86, 2004.
11. M.-L. Li, P. Ramachandran, S. K. Sahoo, S. V. Adve, V. S. Adve, and Y. Zhou. Understanding the propagation of hard errors to software and implications for resilient system design. In 16th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 265-276, 2008.
12. X. Li and D. Yeung. Application-level correctness and its impact on fault tolerance. In Proc. of the 13th International Symposium on High-Performance Computer Architecture, pages 181-192, Feb. 2007.
13. T. May and M. Woods. Alpha-particle-induced soft errors in dynamic memories. IEEE Transactions on Electron Devices, 26(1):2-9, Jan. 1979.
14. S. McCamant and M. D. Ernst. Quantitative information flow as network flow capacity. In Proc. of the SIGPLAN '08 Conference on Programming Language Design and Implementation, pages 193-205, June 2008.
15. A. Meixner, M. Bauer, and D. Sorin. Argus: Low-cost, comprehensive error detection in simple cores. IEEE Micro, 28(1):52-59, 2008.
16. P.Montesinos, W. Liu, and J. Torrellas. Using register lifetime predictions to protect register files against soft errors. In Proc. of the 2007 International Conference on Dependable Systems and Networks, pages 286-296, 2007.
17. S. S. Mukherjee, M. Kontz, and S. K. Reinhardt. Detailed design and evaluation of redundant multithreading alternatives. In Proc. of the 29th Annual International Symposium on Computer Architecture, pages 99-110, 2002. (Pubitemid 34691854)
18. S. S. Mukherjee, C. Weaver, J. Emer, S. Reinhardt, and T. Austin. A systematic methodology to compute the architectural vulnerability factors for a high performance microprocessor. In International Symposium on Microarchitecture, pages 29-42, Dec. 2003.
19. N. Oh, S.Mitra, and E. J.McCluskey. Ed4i: Error detection by diverse data and duplicated instructions. IEEE Transactions on Computers, 51(2):180-199, 2002. (Pubitemid 34198185)
20. P. Racunas, K. Constantinides, S. Manne, and S. Mukherjee. Perturbation-based fault screening. In Proc. of the 13th International Symposium on High-Performance Computer Architecture, pages 169-180, Feb. 2007.
21. V. Reddy, S. Parthasarathy, and E. Rotenberg. Understanding prediction-based partial redundant threading for low-overhead, high-coverage fault tolerance. In 14th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 83-94, Oct. 2006.
22. V. Reddy and E. Rotenberg. Inherent time redundancy (itr): Using program repetition for low-overhead fault tolerance. In Proc. of the 2007 International Conference on Dependable Systems and Networks, pages 307-316, June 2007.
23. V. Reddy and E. Rotenberg. Coverage of a microarchitecture-level fault check regimen in a superscalar processor. In Proc. of the 2008 International Conference on Dependable Systems and Networks, pages 1-10, June 2008.
24. S. K. Reinhardt and S. S. Mukherjee. Transient fault detection via simulataneous multithreading. In Proc. of the 27th Annual International Symposium on Computer Architecture, pages 25-36, June 2000.
25. G. Reis, J. Chang, N. Vachharajani, R. Rangan, and D. I. August. SWIFT: Software implemented fault tolerance. In Proc. of the 2005 International Symposium on Code Generation and Optimization, pages 243-254, 2005.
26. G. A. Reis, J. Chang, N. Vachharajani, R. Rangan, D. I. August, and S. S. Mukherjee. Software-controlled fault tolerance. ACM Transactions on Architecture and Code Optimization, 2(4):366-396, 2005.
27. E. Rotenberg. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In International Symposium on Fault Tolerant Computing, pages 84-91, 1999.
28. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 45-57, New York, NY, USA, 2002. ACM.
29. P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi. Modeling the effect of technology trends on the soft error rate of combinational logic. In Proc. of the 2002 International Conference on Dependable Systems and Networks, pages 389-398, June 2002.
30. J. Smolens, J. Kim, J. Hoe, and B. Falsafi. Efficient resource sharing in concurrent error detecting superscalar microarchitectures. In Proc. of the 37th Annual International Symposium on Microarchitecture, pages 256-268, Dec. 2004.
31. J. C. Smolens, B. T. Gold, B. Falsafi, and J. C. Hoe. Reunion: Complexity-effective multicore redundancy. In Proc. of the 39th Annual International Symposium on Microarchitecture, pages 223-234, 2006.
32. L. Spainhower and T. Gregg. IBM S/390 Parallel Enterprise Server G5 Fault Tolerance: A Historical Perspective. IBM Journal of Research and Development, 43(6):863-873, 1999. (Pubitemid 30589652)
33. N. Vachharajani, M. J. Bridges, J. Chang, R. Rangan, G. Ottoni, J. A. Blome, G. A. Rei, M. Vachharajani, and D. I. August. Rifle: An architectural framework for user-centric information-flow security. In Proc. of the 37th Annual International Symposium on Microarchitecture, pages 243-254, Dec. 2004.
34. C. Wang, H. seop Kim, Y. Wu, and V. Ying. Compiler-managed software-based redundant multi-threading for transient fault detection. In Proc. of the 2007 International Symposium on Code Generation and Optimization, 2007.
35. N. Wang and S. Patel. Restore: Symptom based soft error detection in microprocessors. In International Conference on Dependable Systems and Networks, pages 30-39, June 2005.
36. N. J.Wang, M. Fertig, and S. J. Patel. Y-branches: When you come to a fork in the road, take it. In Proc. of the 12th International Conference on Parallel Architectures and Compilation Techniques, pages 56-65, 2003.
37. N. J. Wang and S. J. Patel. ReStore: Symptom-based soft error detection in microprocessors. IEEE Transactions on Dependable and Secure Computing, 3(3):188-201, June 2006.
38. N. J. Wang, J. Quek, T. M. Rafacz, and S. J. Patel. Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline. In International Conference on Dependable Systems and Networks, page 61, June 2004.
39. C. Weaver and T.M. Austin. A fault tolerant approach to microprocessor design. In Proc. of the 2001 International Conference on Dependable Systems and Networks, pages 411-420, Washington, DC, USA, 2001. IEEE Computer Society.
40. P. M. Wells, K. Chakraborty, and G. S. Sohi. Mixed-mode multicore reliability. In 17th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 169-180, 2009.
41. M. T. Yourst. Ptlsim: A cycle accurate full system x86-64 microarchitectural simulator. In Proc. of the 2007 IEEE Symposium on Performance Analysis of Systems and Software, pages 23-34, 2007.
42. J. F. Ziegler and H. Puchner. SER-History, Trends, and Challenges: A Guide for Designing with Memory ICs. Cypress Semiconductor Corp., 2004.