메뉴 건너뛰기




Volumn 28, Issue 1, 2008, Pages 52-59

Argus: Low-cost, comprehensive error detection in simple cores

Author keywords

Dependability; Error detection; Fault tolerance; Microarchitecture

Indexed keywords

COMPUTATION THEORY; ERROR DETECTION; MICROPROCESSOR CHIPS; MICROPROGRAMMING; STORAGE ALLOCATION (COMPUTER);

EID: 41349107838     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2008.3     Document Type: Article
Times cited : (38)

References (12)
  • 1
    • 41349111229 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors, 2003; http:// www.itrs.net.
    • (2003)
  • 3
    • 0003246550 scopus 로고    scopus 로고
    • DIVA: A Dynamic Approach to Microprocessor Verification
    • May
    • T.M. Austin, "DIVA: A Dynamic Approach to Microprocessor Verification," J. Instruction-Level Parallelism, vol. 2, May 2000; http://www.jilp.org/vol2/v2paper7.pdf.
    • (2000) J. Instruction-Level Parallelism , vol.2
    • Austin, T.M.1
  • 4
    • 0026618728 scopus 로고
    • Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Microprocessors
    • IEEE Press
    • X. Delord and G. Saucier, "Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Microprocessors," Proc. Int'l Test Conf. (ITC 91), IEEE Press, 1991, pp. 936-945.
    • (1991) Proc. Int'l Test Conf. (ITC 91) , pp. 936-945
    • Delord, X.1    Saucier, G.2
  • 7
    • 33845567239 scopus 로고    scopus 로고
    • Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures
    • IEEE CS Press
    • A. Meixner and D.J. Sorin, "Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures," Proc. Int'l Conf. Dependable Systems and Networks, (DSN 06), IEEE CS Press, 2006, pp. 73-82.
    • (2006) Proc. Int'l Conf. Dependable Systems and Networks, (DSN 06) , pp. 73-82
    • Meixner, A.1    Sorin, D.J.2
  • 10
    • 0742310649 scopus 로고    scopus 로고
    • Developing Standard Cells for TSMC 0.25 μm Technology under MOSIS DEEP Rules,
    • VISC-2003-01, Dept. of Electrical and Computer Engineering, Virginia Polytechnic Institute and State Univ
    • J.B. Sulistyo, J. Perry, and D.S. Ha, "Developing Standard Cells for TSMC 0.25 μm Technology under MOSIS DEEP Rules," tech. report VISC-2003-01, Dept. of Electrical and Computer Engineering, Virginia Polytechnic Institute and State Univ., 2003.
    • (2003) tech. report
    • Sulistyo, J.B.1    Perry, J.2    Ha, D.S.3
  • 11
    • 0003650381 scopus 로고
    • An Enhanced Access and Cycle Time Model for On-Chip Caches,
    • 93/5, DEC Western Research Laboratory, July
    • S.J. Wilton and N.P. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," research report 93/5, DEC Western Research Laboratory, July 1994; http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-93-5.pdf.
    • (1994) research report
    • Wilton, S.J.1    Jouppi, N.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.