Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2006, Pages 83-94

  Reddy, Vimal K ^a   Rotenberg, Eric ^a   Parthasarathy, Sailashri ^b  

^a North Carolina State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Branch prediction; Chip multiprocessor (CMP); Redundant multithreading; Simultaneous multithreading (SMT); Slipstream processor; Time redundancy; Transient faults; Value prediction

Indexed keywords

BRANCH PREDICTION; REDUNDANT MULTITHREADING; SIMULTANEOUS MULTITHREADING (SMT); SLIPSTREAM PROCESSORS;

APPROXIMATION THEORY; COMPUTER AIDED INSTRUCTION; FAULT DETECTION; MICROPROCESSOR CHIPS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 34547460101     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1168857.1168869     Document Type: Conference Paper

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