Coverage of a microarchitecture-level fault check regimen in a superscalar processor

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2008, Pages 1-10

  Reddy, Vimal ^a   Rotenberg, Eric ^b  

^a QUALCOMM INC   (United States)

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARBITRARY FAULTS; COMMODITY PROCESSORS; DEPENDABLE SYSTEMS; FAULT-TOLERANT; INTERNATIONAL CONFERENCES; MICRO ARCHITECTURES; SUPERSCALAR PROCESSORS;

COST EFFECTIVENESS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; NETWORK PROTOCOLS; QUALITY ASSURANCE; SENSOR NETWORKS; STAGES;

RELIABILITY;

EID: 53349097907     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2008.4630065     Document Type: Conference Paper

References (12)

1. V. Reddy and E. Rotenberg. Inherent Time Redundancy (ITR): Using program repetition for low-overhead fault tolerance. IEEE/IFIP DSN-37, June 2007.
2. V. Reddy, A. Al-Zawawi, E. Rotenberg. Assertion-based microarchitecture design for improved fault tolerance. ICCD 2006.
3. G. Saggese et al. An Experimental Study of Soft Errors in Microprocessors. IEEE Micro., Nov 2005.
4. S. S. Mukherjee et al. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. IEEE MICRO-36, Dec 2003.
5. P. Shivakumar et al. Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic. DSN-32, 2002.
6. Z. Kalbarczyk et al. Hierarchical simulation approach to accurate fault modeling for system dependability evaluation. IEEE Transactions on Software Engineering, Sep/Oct 1999.
7. V. Reddy. Exploiting Microarchitecture Insights for Efficient Fault Tolerance. PhD thesis, ECE Dept., NCSU, July 2007.
8. K. C. Yeager. The MIPS R10000 superscalar processor. IEEE Micro, April 1996.
9. N. Wang and S. Patel. ReStore: Symptom based soft error detection in microprocessors. IEEE DSN-35, Jun 2005.
10. V. Reddy, S. Parthasarathy and E. Rotenberg. Understanding prediction-based partial redundant threading for low-overhead, high-Coverage fault tolerance. ACM ASPLOS-12, Oct 2006.
11. A. Meixner, M. Bauer, D. Sorin. Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. MICRO-40, 2007.
12. A. Meixner and D. Sorin. Error Detection Using Dynamic Dataflow Verification. PACT-16, Sep. 2007.