Improving FPGA performance for carry-save arithmetic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 4, 2010, Pages 578-590

  Parandeh Afshar, Hadi ^a   Verma, Ajay Kumar ^a   Brisk, Philip ^a   Ienne, Paolo ^a  

^a EPFL   (Switzerland)

Author keywords

Carry save arithmetic; Field programmable gate array (FPGA); Generalized parallel counter (GPC)

Indexed keywords

AREA UTILIZATION; CARRY-SAVE; DATA-FLOW TRANSFORMATIONS; DSP APPLICATION; ENERGY CONSUMPTION; HARDWARE COMPILERS; MULTIINPUT; MULTIPLY ACCUMULATIONS; PARALLEL COUNTERS; PROGRAMMABLE COUNTER;

COUNTING CIRCUITS; DIGITAL SIGNAL PROCESSORS; INDUCTION MOTORS; LOGIC GATES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77950296034     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2014380     Document Type: Article

References (45)

1. C.S. Wallace, "Asuggestionforafastmultiplier," IEEETrans. Electron. Comput., vol. EC-13, no.6, p.754, Dec. 1964.
2. L. Dadda, "Some schemes for parallel multipliers," Alta Freq., vol.34, pp. 349-356, Mar. 1965.
3. A. K. Verma, P. Brisk, and P. Ienne, "Data-flow transformations to maximize the use of carry-save representation in arithmetic circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.27, no.10, pp. 1761-1774, Oct. 2008.
4. S. Mirzaei, A. Hosangadi, and R. Kastner, "FPGA implementation of high speed FIR filters using add and shift method," in Proc. Int. Conf. Comput. Des., San Jose, CA, Oct. 2006, pp. 308-313.
5. C.-Y. Chen, S.-Y. Chien, Y.-W. Huang, T.-C. Chen, T.-C. Wang, and L.-G. Chen, "Analysis and architecture design of variable block-size motion estimation for H.264/AVC," IEEE Trans. Circuits Syst. I, Reg. Papers, vol.53, no.2, pp. 578-593, Feb. 2006.
6. S. Sriram, K. Brown, R. Defosseux, F. Moerman, O. Paviot, V. Sundararajan, and A. Gatherer, "A 64 channel programmable receiver chip for 3G wireless infrastructure," in Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, Sep. 2005, pp. 59-62.
7. S. R. Vangal, Y. V. Hoskote, N. Y. Borkar, and A. Alvandpour, "A 6.2-Gflops floating-point multiply-accumulator with conditional normalization," IEEE J. Solid-State Circuits, vol.41, no.10, pp. 2314-2323, Oct. 2006.
8. A. Shams, W. Pan, A. Chandanandan, and M. Bayoumi, "A high-performance 1D-DCT architecture," in Proc. IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 2000, vol.5, pp. 521-524.
9. H. Parandeh-Afshar, P. Brisk, and P. Ienne, "Efficient synthesis of compressor trees on FPGAs," in Proc. Asia-South Pacific Des. Autom. Conf., Seoul, Korea, Jan. 2008, pp. 138-143.
10. H. Parandeh-Afshar, P. Brisk, and P. Ienne, "Improving synthesis of compressor trees on FPGAs via integer linear programming," in Proc. Int. Conf. Des. Autom. Test Eur., Munich, Germany, Mar. 2008, pp. 1256-1261.
11. I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.26, no.2, pp. 203-215, Feb. 2007.
12. P. Brisk, A. K. Verma, P. Ienne, and H. Parandeh-Afshar, "Enhancing FPGA performance for arithmetic circuits," in Proc. Des. Autom. Conf., San Diego, CA, Jun. 2007, pp. 404-409.
13. W. J. Stenzel, W. J. Kubitz, and G. H. Garcia, "A compact high-speed parallel multiplication scheme," IEEE Trans. Comput., vol.C-26, no.10, pp. 948-957, Oct. 1977.
14. S. Dormido and M. A. Canto, "Synthesis of generalized parallel counters," IEEE Trans. Comput., vol.C-30, no.9, pp. 699-703, Sep. 1981.
15. S. Dormido and M. A. Canto, "An upper bound for the synthesis of generalized parallel counters," IEEE Trans. Comput., vol.C-31, no.8, pp. 802-805, Aug. 1982.
16. "Stratix III Device Handbook, Vol. 1 and 2" Altera Corporation, San Jose, CA, Feb. 2009. [Online]. Available: http://www.altera.com/
17. "Virtex-5 User Guide" Xilinx Corporation, San Jose, CA, 2007. [Online]. Available: http://www.xilinx.com/
18. "Virtex-5 FPGA Xtreme DSP Design Considerations" Xilinx Corporation, San Jose, CA, Jan. 2009. [Online]. Available: http://www.xilinx. com/
19. P. S. Zuchowski, C. B. Reynolds, R. J. Grupp, S. G. Davis, B. Cremen, and B. Troxel, "A hybrid ASIC and FPGA architecture," in Proc. Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 2002, pp. 187-194.
20. P. Jamieson and J. Rose, "Architecting hard crossbars on FPGAs and increasing their area-efficiency with shadow clusters," in Proc. IEEE Int. Conf. Field Programmable Technol., Kitakyushu, Japan, Dec. 2007, pp. 57-64.
21. M. J. Beauchamp, S. Hauck, K. D. Underwood, and K. S. Hemmert, "Architectural modifications to enhance the floating-point performance of FPGAs," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.16, no.2, pp. 177-187, Feb. 2008.
22. R. Kastner, A. Kaplan, S. O. Memik, and E. Bozorgzadeh, "Instruction generation for hybrid-reconfigurable systems," ACM Trans. Des. Autom. Electron. Syst., vol.7, no.4, pp. 602-627, Oct. 2002.
23. A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, A. K. Verma, P. Brisk, F. Gurkaynak, Y. Leblebici, and P. Ienne, "Architecture improvements for field programmable counter arrays: Enabling synthesis of fast compressor trees on FPGAs," in Proc. Int. Symp. FPGAs, Monterey, CA, Feb. 2008, pp. 181-190.
24. D. Cherepacha and D. Lewis, "DP-FPGA: An FPGA architecture optimized for datapaths," VLSI Des., vol.4, no.4, pp. 329-343, 1996.
25. A. Kaviani, D. Vranseic, and S. Brown, "Computational field programmable architecture," in Proc. IEEE Custom Integr. Circuits Conf., Santa Clara, CA, May 1998, pp. 261-264.
26. S. Hauck, M. M. Hosler, and T. W. Fry, "High-performance carry chains for FPGAs," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.8, no.2, pp. 138-147, Apr. 2000.
27. K. Leijten-Nowak and J. L. van Meerbergen, "An FPGA architecture with enhanced datapath functionality," in Proc. Int. Symp. Field Programmable Gate Arrays, Monterey, CA, Feb. 2003, pp. 195-204.
28. M. T. Frederick and A. K. Somani, "Multi-bit carry chains for high-performance reconfigurable fabrics," in Proc. Int. Conf. Field Programmable Logic Appl., Madrid, Spain, Aug. 2006, pp. 1-6.
29. H. Parandeh-Afshar, P. Brisk, and P. Ienne, "A novel FPGA logic block for improved arithmetic performance," in Proc. Int. Symp. Field Programmable Gate Arrays, Monterey, CA, Feb. 2008, pp. 171-180.
30. B. Parhami, "Configurable arithmetic arrays with data-driven control," in Proc. Asilomar Conf. Signals, Syst., Comput., Pacific Grove, CA, Oct./Nov. 2000, pp. 89-93.
31. R. Francis, S. Moore, and R. Mullins, "A network of time-division multiplexed wiring for FPGAs," in Proc. 2nd IEEE Symp. Networks-on-Chip, Apr. 2008, pp. 35-44, Newcastle University, U.K..
32. N. L. Miller and S. F. Quigley, "A novel field programmable gate array architecture for high speed arithmetic processing," in Proc. 8th Int. Workshop Field-Programmable Logic Appl., Tallinn, Estonia, Aug./ Sep. 1998, pp. 386-390.
33. A. Marshall, T. Stansfield, I. Kostarnov, J. Vuillemin, and B. Hutchings, "A reconfigurable arithmetic array for multimedia applications," in Proc. Int. Symp. Field Programmable Gate Arrays, Monterey, CA, Feb. 1999, pp. 135-143.
34. S. Fiske and W. J. Dally, "The reconfigurable arithmetic processor," in Proc. 15th Int. Symp. Comput. Archit., Honolulu, HI, May/Jun. 1988, pp. 30-36.
35. Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar, "A 5-GHz mesh interconnect for a teraflops processor," IEEE Micro, vol.27, no.5, pp. 51-61, Sep./Oct. 2007.
36. J. Cong and H. Huang, "Technology mapping and architecture evaluation for k/m-macrocell-based FPGAs," ACM Trans. Des. Autom. Electron. Syst., vol.10, no.1, pp. 3-23, Jan. 2005.
37. Y. Hu, S. Das, S. Trimberger, and L. He, "Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates," in Proc. Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 2007, pp. 188-193.
38. V. Betz and J. Rose, "VPR:A newpacking, placement, and routing tool for FPGA research," in Proc. 7th Int. Workshop Field-Programmable Logic Appl., London, U.K., Sep. 1997, pp. 213-222.
39. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep Submicron FPGAs. Norwell, MA: Kluwer, Feb. 1999.
40. K. K. W. Poon, S. J. E.Wilton, and A.Yan, "A detailed power model for field-programmable gate arrays," ACM Trans. Des. Autom. Electron. Syst., vol.10, no.2, pp. 279-302, Apr. 2005.
41. N. C. K. Choy and S. J. E. Wilton, "Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs," in Proc. IEEE Int. Conf. Field Programmable Technol., Bangkok, Thailand, Dec. 2006, pp. 253-256.
42. J. Lamoureux and S. J. E. Wilton, "Activity estimation for field programmable gate arrays," in Proc. IEEE Int. Conf. Field Programmable Logic Appl., Madrid, Spain, Aug. 2006, pp. 1-8.
43. F. N. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.2, no.4, pp. 446-455, Dec. 1994.
44. C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "MediaBench: A tool for evaluating and synthesizing multimedia and communications systems," in Proc. 30th Int. Symp. Microarchitecture, Research Triangle Park, NC, Dec. 1997, pp. 330-335.
45. "Creating High-Speed Data Path Components-Application Note," Synopsys Corporation, Mountain View, CA, Oct. 1999, ver. 1999.10, Chapter 1.