A novel FPGA logic block for improved arithmetic performance

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2008, Pages 171-180

  Parandeh Afshar, Hadi ^a   Brisk, Philip ^a   Ienne, Paolo ^a  

^a EPFL   (Switzerland)

Author keywords

6:2 Compressor; Arithmetic Circuits; Carry chain; Compressor Tree; FPGA; Multi operand Addition

Indexed keywords

6:2 COMPRESSOR; ARITHMETIC CIRCUITS; CARRY-CHAIN; FPGA; MULTI-OPERAND ADDITION;

ADDERS; CARRY LOGIC; CELL MEMBRANES; COMPRESSORS; INTEGRATING CIRCUITS; LOGIC GATES; ROUTING ALGORITHMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 70349314168     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1344671.1344698     Document Type: Conference Paper

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