A hybrid ASIC and FPGA architecture

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 187-194

  Zuchowski, Paul S ^a   Reynolds, Christopher B ^a   Grupp, Richard J ^a   Davis, Shelly G ^b   Cremen, Brendan ^b   Troxel, Bill ^b  

^a IBM MICROELECTRONICS   (United States)

^b XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HYBRID CHIP ARCHITECTURE; LOGIC PARTITIONING; LOGIC SIMULATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATION; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER SUPPLIES TO APPARATUS; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036907308     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774600     Document Type: Conference Paper

References (24)

1. IBM Microelectronics, SA-12E Databook, April 2002.
2. IBM Microelectronics, ASIC SA-12E Standard Cell/Gate Array Product Brief, June 2002.
3. IBM Microelectronics, SA-27E Databook: Base Library and I/Os, July 2002.
4. IBM Microelectronics, Blue Logic SA-27E ASIC Product Brief, June 2002.
5. IBM Microelectronics, Cu-11 Databook: 12-Track Base Library, June 2002.
6. IBM Microelectronics, Blue Logic Cu-11 ASIC Product Brief, June 2002.
7. IBM Microlectronics, Blue Logic Cu-08 ASIC Product Brief, April 2002.
8. Xilinx Corporation, XC4000E and XC4000X Series Field-Programmable Gate Arrays, Version 1.6, May 1999.
9. Xilinx Corporation, Virtex™ 2.5V Field Programmable Gate Arrays DS003-1, Version 2.5, April 2001.
10. Xilinx Corporation, Virtex-II 1.5V Field Programmable Gate Arrays DS031-1, Version 2.5, April 2001.
11. G.R. Goslin, "A guide to using FPGAS for Application Specific Digital System Processing Performance", Xilinx Corporation, 1995.
12. Semico, "Foundry Wafer Pricing: Fourth Quarter 2001"
13. David E. Lackey et al "Managing Power and Performance for System-on-Chip Designs using Voltage Islands," Proc. ICCAD-2002, Nov. 2002.
14. A.M. Rincon, M. Trick, T. Guzowski, "A proven Methodology for Designing One-Million-Gate ASICs," Proc. IEEE Custom Integrated Circuits Conference, pp. 44-52, May 1996.
15. A.M. Rincon et al, "Design Methodology for IBM ASIC Products," IBM Journal of Research and Development, Volume 40, Number 4, July 1996.
16. K.M. Carrig, N.T. Gargiulo, R.P. Gregor, D.R. Menard, H.E. Reindel, "A New Direction in ASIC High-Performance Clock Methodology," Proc. IEEE Custom Integrated Circuits Conference, May 1998, pp. 593-596.
17. Karen Parnell and Nick Mehta, "Programmable Logic Design Quick Start Hand Book," Second Edition, Jan. 2002.
18. W. E. Donath "Logic Partitioning in Physical Design Automation of VLSI Systems," The Benjamin/Cummings Publisher Company, 1988.
19. International Technology Roadmap for Semiconductors (ITRS) 2000.
20. H. Krupnova, A. Abbara, G. Saucier, "A Hierarchy-Driven FPGA Partitioning Method," Proc. Design Automation Conference, June 1997.
21. "IC Wizard - The Hierarchical Design Planning Tool," © 2002 Monterey Design Systems, Inc., http://www.mondes.com/prod_icw.html
22. "TeraForm® RTL Design Planner for Deep Submicron SOCs," © 2002 Tera Systems, Inc., http://www.terasystems.com/products/datasheet.htm
23. "First Encounter," © 2002 Cadence Design Systems, Inc., http://www.cadence.com/products/first_encounter.html
24. S. Wilton and R. Saleh, "Programmable Logic IP Cores in SoC Design: Opportunities and Challenges," IEEE Custom Integrated Circuits Conference, May 2001.