Analysis and architecture design of variable block-size motion estimation for H.264/AVC

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 3, 2006, Pages 578-593

  Chen, Ching Yeh ^a   Chien, Shao Yi ^a   Huang, Yu Wen ^a   Chen, Tung Chien ^a   Wang, Tu Chih ^a,b   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b Chin Fong Machine Industrial   (Taiwan)

Author keywords

Block matching; H.264 AVC, motion estimation (ME); Variable block size; Very large scale integration (VLSI) architecture

Indexed keywords

ADDERS; BANDWIDTH; BUFFER CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA FLOW ANALYSIS; IMAGE CODING; VLSI CIRCUITS;

BLOCK MATCHING; PIXEL REGISTERS; SUMS OF ABSOLUTE DIFFERENCES (SADS); VARIABLE BLOCK-SIZE MOTION ESTIMATION;

MOTION ESTIMATION;

EID: 33645798888     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.858488     Document Type: Article

References (26)

1. Video Coding for Low Bit Rate Communication, Feb. 1998.
2. Information Technology-Coding of Audio-Visual Objects - Part 2: Visual, ISO/IEC 14 496-2, 1999.
3. S. Srinivasan, J. Hsu, T. Holcomb, K. Mukerjee, S. L. Regunathan, B. Lin, J. Liang, M.-C. Lee, and J. Ribas-Corbera, "Windows media video 9: overview and application," Signal Process.: Image Commun., vol. 19, pp. 851-875, Sep. 2004.
4. Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, May 2003.
5. K. M. Yang, M. T. Sun, and L. Wu, "A family of VLSI designs for the motion compensation block-matching algorithm," IEEE Trans. Circuits Syst., vol. 36, no. 10, pp. 1317-1325, Oct. 1989.
6. T. Komarek and P. Pirsch, "Array architectures for block matching algorithms," IEEE Trans. Circuits Syst., vol. 36, no. 10, pp. 1301-1308, Oct. 1989.
7. H. Yeo and Y. H. Hu, "A novel modular systolic array architecture for full-search block matching motion estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 5, no. 5, pp. 407-416, Oct. 1995.
8. Y. K. Lai and L. G. Chen, "A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm," IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 2, pp. 124-127, Apr. 1998.
9. L. De Vos and M. Stegherr, "Parameterizable VLSI architectures for the full-search block-matching algorithm," IEEE Trans. Circuits Syst., vol. 36, no. 10, pp. 1309-1316, Oct. 1989.
10. C. H. Hsieh and T. P. Lin, "VLSI architecture for block-matching motion estimation algorithm," IEEE Trans. Circuits Syst. Video Technol., vol. 2, no. 2, pp. 169-175, Jun. 1992.
11. J. F. Shen, T. C. Wang, and L. G. Chen, "A novel low-power full search block-matching motion estimation design for H.263+," IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 7, pp. 890-897, Jul. 2001.
12. N. Roma and L. Sousa, "Efficient and configurable full-search blockmatching processors," IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 12, pp. 1160-1167, Dec. 2002.
13. V. L. Do and K. Y. Yun, "A low-power VLSI architecture for full-search block-matching motion estimation," IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 4, pp. 393-398, Aug. 1998.
14. X. Q. Gao, C. J. Duanmu, and C. R. Zou, "A multilevel successive elimination algorithm for block matching motion estimation," IEEE Trans. Image Process., vol. 9, no. 3, pp. 501-504, Mar. 2000.
15. M. Brünig and W. Niehsen, "Fast full-search block matching," IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 2, pp. 241-247, Feb. 2001.
16. S. F. Chang, J. H. Hwang, and C. W. Jen, "Scalable array architecture design for full search block matching," IEEE Trans. Circuits Syst. Video Technol., vol. 5, no. 4, pp. 332-343, Aug. 1995.
17. H. M. Jong, L. G. Chen, and T. D. Chiueh, "Parallel architectures for 3-step hierarchical search block-matching algorithm," IEEE Trans. Circuits Syst. Video Technol., vol. 4, no. 4, pp. 407-416, Aug. 1994.
18. Y. W. Huang, T. C. Wang, B. Y. Hsieh, and L. G. Chen, "Hardware architecture design for variable block-size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264," in Proc. IEEE Int. Symp. Circuits Syst., 2003, pp. 796-799.
19. S. Kittitornkun and Y. H. Hu, "Frame-level pipelined motion estimation array processor," IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 2, pp. 248-251, Feb. 2001.
20. (2003, Aug.) Joint Video Team Reference Software JM7.3. [Online] http://bs.hhi.de/suehring/tml/download/
21. T.-C. Chen, Y.-W. Huang, and L.-G. Chen, "Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture," in Proc. IEEE Int. Symp. Circuits Syst., 2004, pp. 273-276.
22. Y. W. Huang, T. C. Chen, C. H. Tsai, C. Y. Chen, T. W. Chen, C. S. Chen, C. F. Shen, S. Y. Ma, T. C. Wang, B. Y. Hsieh, H. C. Fang, and L. G. Chen, "A 1.3 tops H.264/AVC signle-chip encoder for HDTV applications," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 128-129.
23. T. Koga, K. Iinuma, A. Hirano, Y. Iijima, and T. Ishiguro, "Motion compensated interframe coding for video conferencing," in Proc. Nat. Telecommun. Conf., New Orleans, LA, 1981, pp. G5.3.1-G5.3.5.
24. Z. He and M.-I. Liou, "Reducing hardware complexity of motion estimation algorithms using truncated pixels," in Proc. IEEE Int. Symp. Circuits Syst., 1997, pp. 2809-2812.
25. J. C. Tuan, T. S. Chang, and C. W. Jen, "On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture," IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 1, pp. 61-72, Jan. 2002.
26. M.-Y. Hsu, "Scalable module-based architecture for MPEG-4 BMA motion estimation," master's thesis, Dept. Elect. Eng., National Taiwan Univ., Taipei, Jun. 2000.