Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 188-193

  Hu, Yu ^a,b   Das, Satyaki ^b   Trimberger, Steve ^b   He, Lei ^a  

^a University of California   (United States)

^b XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER-AIDED DESIGN; FPGA APPLICATIONS; INTERNATIONAL CONFERENCES; LOGIC FUNC-TION; LOOK-UP-TABLES; PROGRAMMABLE LOGICS; RESOURCE UTILIZATIONS; TECHNOLOGY-MAPPING;

BOOLEAN FUNCTIONS; CONFORMAL MAPPING; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGER PROGRAMMING; LINEAR PROGRAMMING; LINEARIZATION; MIXING;

MACROS;

EID: 50249128247     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397264     Document Type: Conference Paper

References (27)

1. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999.
2. "The programmable gate array data book," Xilinx Inc., 1989.
3. J. Cong, et al, "Technology mapping and architecture evaluation for k/m-macrocell-based FPGAs," TOADES, 2005.
4. "Xilinx datasheets," http://www.xilinx.com/literature.
5. A. Cosoroaba and F. Rivoallon, "Achieving higher system performance with the virtex-5 family of FPGAs," in http://www.xilinx.com/ literature.
6. F. Li and L. He, "Power modeling and characteristics of field programmable gate arrays," TCAD, 2005.
7. http://iwls.org/iwls2005/benchmarks.html.
8. http://www.eecs.berkeley.edu/ alanmi/abc/.
9. J. Cong and S. Xu, "Delay-optimal technology mapping for FPGAs with heterogeneous LUTs," DAC, 1998.
10. J. Cong, et al, "Cut ranking and pruning: Enabling a general and efficient fpga mapping solution," FPGA, 1999.
11. A. Kaviani and S. Brown, "Hybrid FPGA architecture," FPGA, 1996.
12. J. Cong and Y. Ding, "Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," TCAD, 1994.
13. J. Cong and Y. Ding, "On area/depth trade-off in LUT-based FPGA technology mapping," TVLSI, 1994.
14. D. Chen and J. Cong, "Daomap: A depth-optimal area optimization mapping algorithm for FPGA designs," ICCAD, 2004.
15. V. Manohara-rajah, et al, "Heuristics for area minimization in LUT-based FPGA technology mapping," IWLS, 2004.
16. A. Mishchenko, et al, "Integrating logic synthesis, technology mapping, and retiming," IWLS, 2005.
17. S. Chatterjee, et al, "Factor cuts," ICCAD, 2006.
18. A. Ling, et al, "Fpga logic synthesis using quantified boolean satisfiability," SAT 2005, pp. 444-450.
19. S. Safarpour, et al, "Efficient satbased boolean matching for fpga technology mapping," DAC, 2006.
20. D. Chai and A. Kuehlmann, "Building a better boolean matcher and symmetry detector," DATE, 2006.
21. S. C. Soheil Ghiasi, et al, "A unified theory of timing budget management," DAC 2004.
22. E. M. Sentovich, et al, "SIS: A system for sequential circuit systhesis," Department of Electrical Engineering and Computer Science, Berkeley, CA 94720, 1992.
23. J. M. Rabaey, et al, Digital Integrated Circuits: A Design Perspective (Second Edition). Prentice-Hall, 2003.
24. http://www.mosek.com.
25. http://www.cs.chalmers.se/Cs/Research/FormalMethods/MiniSat/MiniSat. html.
26. Jianshe He, "Technology Mapping and Architecture of Heterogenous Field-Programmable Gate Arrays," M.A.Sc. Thesis, University of Toronto, 1993.
27. Kevin Chung, "Architecture and Synthesis of Field-Programmable Gate Arrays with Hard-wired Connections," Ph.D. Thesis, University of Toronto, 1994.