메뉴 건너뛰기




Volumn 1, Issue , 2000, Pages 89-93

Configurable arithmetic arrays with data-driven control

Author keywords

Bit serial arithmetic; Digit pipelined arithmetic; DSP hardware; FPGA like arrays; On line algorithm; Pipelining; Programmable logic; Redundant number system

Indexed keywords

COMPUTATIONAL COMPLEXITY; DIGITAL SIGNAL PROCESSING; FAULT TOLERANT COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS; FORMAL LOGIC; PIPELINE PROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS;

EID: 0034449694     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (25)
  • 1
  • 15
    • 0033733825 scopus 로고    scopus 로고
    • Accelerating pipelined integer and floating-point accumulations in configurable hardware with delayed addition techniques
    • Mar. 2000
    • (2000) IEEE Trans. Computers , vol.49 , Issue.3 , pp. 208-218
    • Luo, Z.1    Martonosi, M.2
  • 17
    • 84956852816 scopus 로고    scopus 로고
    • A novel field programmable gate array architecture for high speed arithmetic processing
    • Hart98
    • Miller, N.L.1    Quigley, S.F.2
  • 19
    • 0025210204 scopus 로고
    • Generalized signed-digit number systems: A unifying framework for redundant number representations
    • Jan.
    • (1990) IEEE Trans. Computers , vol.39 , pp. 89-98
    • Parhami, B.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.