Enhancing FPGA performance for arithmetic circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 334-337

  Brisk, Philip ^a   Verma, Ajay K ^a   Ienne, Paolo ^a   Parandeh Afshar, Hadi ^a,b  

^a EPFL   (Switzerland)

^b UNIVERSITY OF TEHRAN   (Iran)

Author keywords

Compressor tree; Field Programmable Counter Array (FPCA) look up Table (LUT); Field Programmable Gate Array (fpga)

Indexed keywords

CIRCUIT SIMULATION; COST EFFECTIVENESS; DECISION TABLES; DIGITAL ARITHMETIC; ENERGY EFFICIENCY; INTEGRATED CIRCUIT LAYOUT;

COMPRESSOR TREE; FIELD PROGRAMMABLE COUNTER ARRAY (FPCA) LOOK-UP TABLE (LUT;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34547268739     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375182     Document Type: Conference Paper

References (15)

1. Altera Corporation. Stratix II vs. Virtex-4 Performance Comparison, v. 2.0. White paper. September, 2006.
2. Betz, V., Rose, J., and Marquardt, A. Architecture and CAD for Deep Submicron FPGAs, Kluwer Academic Publishers, 1999.
3. Ereegovac, M., D., and Lang, T. Digital Arithmetic, Morgan-Kauffman, San Francisco, CA, USA, 2004.
4. Lewis, D., et al. The Stratix II logic and routing architecture. Int. Symp. Field Prog. Gate Arrays (FPGA '05) (Monterey, CA, USA, February 20-22, 2005) 14-20.
5. Mirzaei, S., Hosangadi, A., and Kastner, R. FPGA implementation of high speed fir filters using add and shift method. Int. Conf. Computed Design (ICCD '06), (San Jose, CA, USA, October 1-4, 2006)
6. Parhami, B. Computer Arithmetic: Algorithms and Hardware Designs, Oxford University Press, New York, NY, USA, 2000.
7. Stelling, P. F., Martel, C. U., Oklobdzija, V. G., and Ravi, R. Optimal circuits for parallel multipliers. IEEE Trans. Computers, 47, 3 (March, 1998), 273-285.
8. Verma, A. K., and Ienne, P. Automatic synthesis of compressor trees: reevaluating large counters. Design Automation and Test in Europe (DATE '07) (Nice, France, April 16-20, 2007).
9. Verma, A. K., and Ienne, P. Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. Int. Conf. Computer-Aided Design (ICCAD '04) (San Jose, CA, USA, November 7-11, 2004) 791-798
10. Verma, A. K., and Ienne, P. Improving XOR-dominated arithmetic circuits by exploiting dependencies between operands. Asia and South Pacific Design Automation Conf. (ASP-DAC '07) (Yokohama, Japan, January 23-26, 2007)
11. Wallace, C. S. A suggestion for a fast multiplier, IEEE Trans. Electronic Computers, 13, 1964 14-17
12. Wiegand, T., Sullivan, G. J., Bjontegaard, G., and Luthra, A. Overview of the H.264/AVC video coding standard. IEEE Trans. Circuits and Systems for Video Tech., 13, 7 (July, 2003) 560-576
13. Xilinx Corporation. Distributed Arithmetic FIR Filter v. 9.0, Product Specification. 2004.
14. Xilinx Corporation. Virtex-4 User Guide, v. 2.1. White paper.
15. Xilinx Corporation. XtremeDSP for Virtex-4 FPGAs User Guide, v. 2.4. White paper.