Improving synthesis of compressor trees on FPGAs via integer linear programming

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 1256-1261

  Parandeh Afshar, Hadi ^a,b   Brisk, Philip ^b   Ienne, Paolo ^b  

^a UNIVERSITY OF TEHRAN   (Iran)

^b EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPRESSORS; DELAY CIRCUITS; DYNAMIC PROGRAMMING; FEEDBACK CONTROL; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HEURISTIC METHODS; INDUSTRIAL ENGINEERING; INTEGER PROGRAMMING; LINEARIZATION; PARTICLE SIZE ANALYSIS; TABLE LOOKUP; TESTING;

ADDER TREE; ALTERA STRATIX; COMPRESSOR TREE; GREEDY HEURISTIC; INTEGER LINEAR PROGRAMMING; LOOK-UP TABLE; MAPPING PROBLEMS; MULTI-INPUT; NEW APPROACHES; P RIOR WORK; PARALLEL COUNTERS; VIDEO PROCESSING APPLICATIONS;

LINEAR PROGRAMMING;

EID: 49749108872     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484851     Document Type: Conference Paper

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