Architectural modifications to enhance the floating-point performance of FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 2, 2008, Pages 177-187

  Beauchamp, Michael J ^a   Hauck, Scott ^b   Underwood, Keith D ^c,d   Hemmert, K Scott ^c  

^a MIPS Technologies Inc   (United States)

^b University of Washington   (United States)

^c SANDIA NATIONAL LABORATORIES   (United States)

^d INTEL CORPORATION   (United States)

Author keywords

Field programmable gate array (FPGA); Floating point arithmetic; Reconfigurable architecture

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; MULTIPLEXING; TABLE LOOKUP;

ARCHITECTURAL MODIFICATIONS; RECONFIGURABLE ARCHITECTURE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 38349093267     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.912041     Document Type: Article

References (26)

1. K. D. Underwood, "FPGAs vs. CPUs: Trends in peak floating-point performance," in Proc. ACM Int. Symp. Field Program. Gate Arrays, 2004, pp. 171-180.
2. K. D. Underwood and K. S. Hemmert, "Closing the gap: CPU and FPGA trends in sustainable floating-point BLAS performance," in Proc. IEEE Symp. FPGAs Custom Comput. Mach., 2004, pp. 219-228.
3. K. S. Hemmert and K. D. Underwood, "An analysis of the double-precision floating-point FFT on FPGAs," in Proc. IEEE Symp. FPGAs Custom Comput. Mach., 2005, pp. 171-180.
4. M. de Lorimier and A. DeHon, "Floating point sparse matrix-vector multiply for FPGAs," in Proc. ACM Int. Symp. Field Program. Gate Arrays, 2005, pp. 75-85.
5. G. Govindu, S. Choi, V. K. Prasanna, V. Daga, S. Gangadharpalli, and V. Sridhar, "A high-performance and energy efficient architecture for floating-point based lu decomposition on fpgas," in Proc. 11th Reconfigurable Arch. Workshop (RAW), 2004, p. 149.
6. L. Zhuo and V. K. Prasanna, "Scalable and modular algorithms for floating-point matrix multiplication on FPGAs," in Proc. 18th Int. Parallel Distrib. Process. Symp. (IPDPS), 2004, pp. 433-448.
7. L. Zhuo and V. K. Prasanna, "Sparse matrix-vector multiplication on FPGAs," in Proc. ACM Int. Symp. Field Program. Gate Arrays, 2005, pp. 63-74.
8. "IEEE standard for binary floating-point arithmetic,", ANSI/IEEE Std. 754-1985, 1985.
9. K. S. Hemmert and K. D. Underwood, "Open source high performance floating-point modules," in Proc. IEEE Symp. FPGAs Custom Comput. Mach., 2006, pp. 349-350.
10. I. Koren, Computer Arithmetic Algorithms, 2nded. Natick, MA: A.K. Peters, Ltd., 2002.
11. Xilinx, San Jose, CA, "Virtex-II Pro and Virtex-II Pro X platform FPGAs: Complete data sheet," Jun. 2005 [Online]. Available: http://direct.xilinx.com/bvdocs/publications/ds083.pdf
12. Xilinx, San Jose, CA, "Virtex-4 family overview," Jun. 2005 [Online]. Available: http://direct.xilinx.com/bvdocs/publications/ds.112.pdf
13. V. Betz and J. Rose, "VPR: A new packing, placement and routing tool for FPGA research," in Proc. 7th Int. Workshop Field-Program. Logic Appl., 1997, pp. 213-222.
14. V. Betz and J. Rose, Architecture and CAD for Deep-Submicron FPGAs. Boston, MA: Kluwer, 1999.
15. Xilinx, San Jose, CA, "Xilinx: ASMBL architecture," 2005 [On-line]. Available: http://www.xilinx.com/products/silicon_solutions/fpgas/ virtex/virtex4/overview/
16. Xilinx, San Jose, CA, "Virtex-4 data sheet: DC and switching characteristics," Aug. 2005 [Online]. Available: http://direct.xilinx.com/ bv-docs/publications/ds302.pdf
17. Xilinx, San Jose, CA, "Virtex-II platform FPGAs: Complete data sheet," Mar. 2005 [Online]. Available: http://direct.xilinx.com/bv-docs/ publications/ds031. pdf
18. MIPS Technologies, Inc., Mountain View, CA, "64-Bit Cores, MIPS64 Family Features," 2005 [Online]. Available: http://www.mips.com/content/ Products/Cores/64-BitCores
19. J. B. Brockman, S. Thoziyoor, S. Kuntz, and P. Kogge, "A low cost, multithreaded processing-in-memory system," in Proc. 3rd Workshop Memory Performance Issues, 2004, pp. 16-22.
20. B. Hutchings, P. Bellows, J. Hawkins, K. S. Hemmert, B. Nelson, and M. Rytting, "A CAD suite for high-performance FPGA design," in Proc. IEEE Workshop FPGAs Custom Comput. Mach., 1999, pp. 12-24.
21. E. Sentovich et al., "SIS: A system for sequential circuit analysis," Univ. California, Berkeley, Tech Rep. UCB/ERL M92/41, 1992.
22. J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 13, no. 1, pp. 1-12, Jan. 1994.
23. A. Ye and J. Rose, "Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits," in Proc. ACM Int. Symp. Field-Program. Gate Arrays, 2005, pp. 3-13.
24. D. Lewis et al., "The stratix II logic and routing architecture," in Proc. ACM Int. Symp. Field-Program, Gate Arrays, 2005, pp. 14-20.
25. Xilinx, San Jose, CA, "Virtex-5 LX platform overview," 2006 [Online]. Available: http://direct.xilinx.com/bvdocs/publications/ds100.pdf
26. Xilinx, San Jose, CA, "Xilinx ISE 6 software manuals," 2007 [On-line]. Available: http://toolbox.xilinx.com/docsan/xilinx6/books/manuals.pdf