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Volumn 7, Issue 4, 2002, Pages 605-627

Instruction generation for hybrid reconfigurable systems

Author keywords

FPGA; High level synthesis; Reconfigurable computing

Indexed keywords

ALGORITHMS; DATA FLOW ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; GRAPH THEORY; ITERATIVE METHODS;

EID: 0036826798     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/605440.605446     Document Type: Article
Times cited : (150)

References (42)
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  • 3
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    • SPS: Strategically programmable system-fully automated architecture generation and application compilation
    • BOZORGZADEH, B., OGRENCI MEMIK, S., KASTNER, R., AND SARRAFZADEH, M. 2002b. SPS: Strategically programmable system-fully automated architecture generation and application compilation. Tech. Rep. UCLA.
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    • The Garp architecture and C compiler
    • CALLAHAN, T. J., HAUSER, J. R., AND WAWRZYNEK, J. 2000. The Garp architecture and C compiler. Computer 33, 4, 62-69.
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    • Callahan, T.J.1    Hauser, J.R.2    Wawrzynek, J.3
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    • 0033884908 scopus 로고    scopus 로고
    • Xtensa: A configurable and extensible processor
    • GONZALEZ, R. E. 2000. Xtensa: A configurable and extensible processor. IEEE Micro 20, 2, 60-70.
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    • Gonzalez, R.E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.