-
1
-
-
0029255778
-
Real-time image processing on a custom computing platform
-
ATHANAS, P. M. AND ABBOTT, A. L. 1995. Real-time image processing on a custom computing platform. Computer 28, 2, 16-25.
-
(1995)
Computer
, vol.28
, Issue.2
, pp. 16-25
-
-
Athanas, P.M.1
Abbott, A.L.2
-
2
-
-
33645750898
-
Pattern selection: Customized block allocation for domain-specific programmable systems
-
BOZORGZADEH, E., OGRENCI MEMIK, S., KASTNER, R., AND SARRAFZADEH, M. 2002a. Pattern selection: Customized block allocation for domain-specific programmable systems. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms.
-
(2002)
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms
-
-
Bozorgzadeh, E.1
Ogrenci Memik, S.2
Kastner, R.3
Sarrafzadeh, M.4
-
3
-
-
0013504441
-
SPS: Strategically programmable system-fully automated architecture generation and application compilation
-
BOZORGZADEH, B., OGRENCI MEMIK, S., KASTNER, R., AND SARRAFZADEH, M. 2002b. SPS: Strategically programmable system-fully automated architecture generation and application compilation. Tech. Rep. UCLA.
-
(2002)
Tech. Rep. UCLA
-
-
Bozorgzadeh, B.1
Ogrenci Memik, S.2
Kastner, R.3
Sarrafzadeh, M.4
-
5
-
-
0031645164
-
Fast module mapping and placement for datapaths in FPGAs
-
CALLAHAN, T. J., CHONG, P., DEHON, A., AND WAWRZYNEK, J. 1998. Fast module mapping and placement for datapaths in FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays.
-
(1998)
Proceedings of the International Symposium on Field Programmable Gate Arrays
-
-
Callahan, T.J.1
Chong, P.2
Dehon, A.3
Wawrzynek, J.4
-
6
-
-
0034174174
-
The Garp architecture and C compiler
-
CALLAHAN, T. J., HAUSER, J. R., AND WAWRZYNEK, J. 2000. The Garp architecture and C compiler. Computer 33, 4, 62-69.
-
(2000)
Computer
, vol.33
, Issue.4
, pp. 62-69
-
-
Callahan, T.J.1
Hauser, J.R.2
Wawrzynek, J.3
-
7
-
-
0032319163
-
A general approach for regularity extraction in datapath circuits
-
CHOWDHARY, A., KALE, S., SARIPELLA, P., SEHGAL, N., AND GUPTA, R. 1998. A general approach for regularity extraction in datapath circuits. In Proceedings of the International Conference on Computer-Aided Design.
-
(1998)
Proceedings of the International Conference on Computer-Aided Design
-
-
Chowdhary, A.1
Kale, S.2
Saripella, P.3
Sehgal, N.4
Gupta, R.5
-
9
-
-
35048849268
-
Flexible routing architecture generation for domain-specific reconfigurable subsystems
-
COMPTON, K., SHARMA, A., PHILLIPS, S., AND HAUCK, S. 2002. Flexible routing architecture generation for domain-specific reconfigurable subsystems. In Proceedings of the International Symposium on Field Programmable Logic and Applications.
-
(2002)
Proceedings of the International Symposium on Field Programmable Logic and Applications
-
-
Compton, K.1
Sharma, A.2
Phillips, S.3
Hauck, S.4
-
10
-
-
0030211562
-
Performance optimization using template mapping for datapath-intensive high-level synthesis
-
CORAZAO, M. R., KHALAF, M. A., GUERRA, L. M., POTKONJAK, M., AND RABAEY, J. M. 1996. Performance optimization using template mapping for datapath-intensive high-level synthesis. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 15, 8, 877-888.
-
(1996)
IEEE Trans. Comput. Aided Des. Integrated Circ. Syst.
, vol.15
, Issue.8
, pp. 877-888
-
-
Corazao, M.R.1
Khalaf, M.A.2
Guerra, L.M.3
Potkonjak, M.4
Rabaey, J.M.5
-
15
-
-
0003652206
-
-
Kluwer Academic, Boston
-
GAJSKI, D. D., ZHU, J., DÖMER, R., GERSTLAUSER, A., AND ZHOA, S. 2000. SpecC: Specification Language and Methodology. Kluwer Academic, Boston.
-
(2000)
SpecC: Specification Language and Methodology
-
-
Gajski, D.D.1
Zhu, J.2
Dömer, R.3
Gerstlauser, A.4
Zhoa, S.5
-
17
-
-
0032688082
-
Hierarchical finite state machines with multiple concurrency models
-
GIRAULT, A., BILUNG, L., AND LEE, E. A. 1999. Hierarchical finite state machines with multiple concurrency models. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 18, 6, 742-760.
-
(1999)
IEEE Trans. Comput. Aided Des. Integrated Circ. Syst.
, vol.18
, Issue.6
, pp. 742-760
-
-
Girault, A.1
Bilung, L.2
Lee, E.A.3
-
18
-
-
0025807368
-
Building and using a highly parallel programmable logic array
-
GOKHALE, M., HOLMES, W., KOPSER, A., LUCAS, S., MINNICH, R., SWEELY, D., AND LOPRESTI, D. 1991. Building and using a highly parallel programmable logic array. Computer 24, 1, 81-89.
-
(1991)
Computer
, vol.24
, Issue.1
, pp. 81-89
-
-
Gokhale, M.1
Holmes, W.2
Kopser, A.3
Lucas, S.4
Minnich, R.5
Sweely, D.6
Lopresti, D.7
-
19
-
-
0034174187
-
PipeRench: A reconfigurable architecture and compiler
-
GOLDSTEIN, S. C., SCHMIT, H., BUDIU, M., CADAMBI, S., MOE, M., AND TAYLOR, R. R. 2000. PipeRench: A reconfigurable architecture and compiler. Computer 33, 4, 70-77.
-
(2000)
Computer
, vol.33
, Issue.4
, pp. 70-77
-
-
Goldstein, S.C.1
Schmit, H.2
Budiu, M.3
Cadambi, S.4
Moe, M.5
Taylor, R.R.6
-
20
-
-
0033884908
-
Xtensa: A configurable and extensible processor
-
GONZALEZ, R. E. 2000. Xtensa: A configurable and extensible processor. IEEE Micro 20, 2, 60-70.
-
(2000)
IEEE Micro
, vol.20
, Issue.2
, pp. 60-70
-
-
Gonzalez, R.E.1
-
22
-
-
0030380793
-
Maximizing multiprocessor performance with the SUIF compiler
-
HALL, M. W., ANDERSON, J. M., AMARASINGHE, S. P., MURPHY, B. R., SHIH-WEI, L., BUGNION, E., AND LAM, M. S. 1996. Maximizing multiprocessor performance with the SUIF compiler. Computer 29, 12, 84-89.
-
(1996)
Computer
, vol.29
, Issue.12
, pp. 84-89
-
-
Hall, M.W.1
Anderson, J.M.2
Amarasinghe, S.P.3
Murphy, B.R.4
Shih-Wei, L.5
Bugnion, E.6
Lam, M.S.7
-
23
-
-
0000504010
-
The Chimaera reconfigurable functional unit
-
HAUCK, S., FRY, T. W., HOSLER, M. M., AND KAO, J. P. 1997. The Chimaera reconfigurable functional unit. In Proceedings of the Symposium on Field-Programmable Custom Computing Machines.
-
(1997)
Proceedings of the Symposium on Field-Programmable Custom Computing Machines
-
-
Hauck, S.1
Fry, T.W.2
Hosler, M.M.3
Kao, J.P.4
-
25
-
-
0013534973
-
Compiler techniques for system synthesis optimization
-
KASTNER, R., BOZORGZADEH, E., OGRENCI MEMIK, S., AND SARRAFZADEH, M. 2002. Compiler techniques for system synthesis optimization, Tech. Rep. UCLA.
-
(2002)
Tech. Rep. UCLA
-
-
Kastner, R.1
Bozorgzadeh, E.2
Ogrenci Memik, S.3
Sarrafzadeh, M.4
-
26
-
-
0035211904
-
Instruction generation for hybrid reconfigurable systems
-
KASTNER, R., OGRENCI MEMIK, S., BOZORGZADEH, E., AND SARRAFZADEH, M. 2001. Instruction generation for hybrid reconfigurable systems. In Proceedings of the International Conference on Computer Aided Design.
-
(2001)
Proceedings of the International Conference on Computer Aided Design
-
-
Kastner, R.1
Ogrenci Memik, S.2
Bozorgzadeh, E.3
Sarrafzadeh, M.4
-
29
-
-
0029202471
-
A comparison of full and partial predicated execution support for ILP processors
-
MAHLKE, S. A., HANK, R. E., McCORMICK, J. E., AUGUST, D. I., AND HWU, W. W. 1995. A comparison of full and partial predicated execution support for ILP processors. In Proceedings of the International Symposium on Computer Architecture.
-
(1995)
Proceedings of the International Symposium on Computer Architecture
-
-
Mahlke, S.A.1
Hank, R.E.2
McCormick, J.E.3
August, D.I.4
Hwu, W.W.5
-
30
-
-
0026980852
-
Effective compiler support for predicated execution using the hyperblock
-
MAHLKE, S. A., LIN, D. C., CHEN, W. Y., HANK, R. E., AND BRINGMANN, R. A. 1992. Effective compiler support for predicated execution using the hyperblock. In Proceedings of the International Symposium on Microarchitecture.
-
(1992)
Proceedings of the International Symposium on Microarchitecture
-
-
Mahlke, S.A.1
Lin, D.C.2
Chen, W.Y.3
Hank, R.E.4
Bringmann, R.A.5
-
33
-
-
0026174923
-
Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications
-
NOTE, S., GEURTS, W., CATTHOOR, F., AND DE MAN, H. 1991. Cathedral-III: architecture-driven high-level synthesis for high throughput DSP applications. In Proceedings of the Design Automation Conference.
-
(1991)
Proceedings of the Design Automation Conference
-
-
Note, S.1
Geurts, W.2
Catthoor, F.3
De Man, H.4
-
34
-
-
0003296793
-
Strategically programmable systems
-
OGRENCI MEMIK, S., BOZORGZADEH, E., KASTNER, R., AND SARRAFZADEH, M. 2001a. Strategically programmable systems. In Proceedings of the Reconfigurable Architecture Workshop.
-
(2001)
Proceedings of the Reconfigurable Architecture Workshop
-
-
Ogrenci Memik, S.1
Bozorgzadeh, E.2
Kastner, R.3
Sarrafzadeh, M.4
-
35
-
-
0035215647
-
A super-scheduler for embedded reconfigurable systems
-
OGRENCI MEMIK, S., BOZORGZADEH, E., KASTNER, R., AND SARRAFZADEH, M. 2001b. A super-scheduler for embedded reconfigurable systems. In Proceedings of the International Conference on Computer Aided Design.
-
(2001)
Proceedings of the International Conference on Computer Aided Design
-
-
Ogrenci Memik, S.1
Bozorgzadeh, E.2
Kastner, R.3
Sarrafzadeh, M.4
-
36
-
-
0032671229
-
Using configurable computing to accelerate Boolean satisfiability
-
PEIXIN, Z., MARTONOSI, M., ASHAR, P., AND MALIK, S. 1999. Using configurable computing to accelerate Boolean satisfiability. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 18, 6, 861-868.
-
(1999)
IEEE Trans. Comput. Aided Des. Integrated Circ. Syst.
, vol.18
, Issue.6
, pp. 861-868
-
-
Peixin, Z.1
Martonosi, M.2
Ashar, P.3
Malik, S.4
-
38
-
-
0033713032
-
High-level synthesis of nonprogrammable hardware accelerators
-
SCHREIBER, R., ADITYA, S., RAU, B. R., KATHAIL, V., MAHLKE, S., ABRAHAM, S., AND SNIDER, G. 2000. High-level synthesis of nonprogrammable hardware accelerators. In Proceedings of the International Conference on Application-Specific Systems, Architectures, and Processors.
-
(2000)
Proceedings of the International Conference on Application-Specific Systems, Architectures, and Processors
-
-
Schreiber, R.1
Aditya, S.2
Rau, B.R.3
Kathail, V.4
Mahlke, S.5
Abraham, S.6
Snider, G.7
-
41
-
-
0029227122
-
Scheduling using behavioral templates
-
TAI, L., KNAPP, D., MILLER, R., AND MACMILLEN, D. 1995. Scheduling using behavioral templates. In Proceedings of the Design Automation Conference.
-
(1995)
Proceedings of the Design Automation Conference
-
-
Tai, L.1
Knapp, D.2
Miller, R.3
Macmillen, D.4
-
42
-
-
0036505033
-
The raw microprocessor: A computational fabric for software circuits and general-purpose programs
-
TAYLOR, M. B., KIM, J., MILLER, J., WENTZLAFF, D., GHODRAT, F., GREENWALD, B., HOFFMAN, H., JOHNSON, P., LEE, J.-W., LEE, W., MA, A., SARAF, A., SENESKI, M., SHNIDMAN, N., STRUMPEN, V., FRANK, M., AMARASINGHE, S., AND AGARWAL, A. 2002. The raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro 22, 2, 25-35.
-
(2002)
IEEE Micro
, vol.22
, Issue.2
, pp. 25-35
-
-
Taylor, M.B.1
Kim, J.2
Miller, J.3
Wentzlaff, D.4
Ghodrat, F.5
Greenwald, B.6
Hoffman, H.7
Johnson, P.8
Lee, J.-W.9
Lee, W.10
Ma, A.11
Saraf, A.12
Seneski, M.13
Shnidman, N.14
Strumpen, V.15
Frank, M.16
Amarasinghe, S.17
Agarwal, A.18
|