A novel field programmable gate array architecture for high speed arithmetic processing

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1482, Issue , 1998, Pages 386-390

  Miller, N L ^a   Quigley, S F ^a  

^a UNIVERSITY OF BIRMINGHAM   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; DATA HANDLING; LOGIC DEVICES; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

ARITHMETIC UNIT; BIT-PARALLEL PROCESSING; FPGA ARCHITECTURES; HIGH PERFORMANCE COMPUTERS; HIGH-SPEED ARITHMETIC; PERFORMANCE CHARACTERISTICS; PROPOSED ARCHITECTURES; RECONFIGURABLE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84956852816     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0055266     Document Type: Conference Paper

References (7)

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