FPGA implementation of high speed FIR filters using add and shift method

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 308-313

  Mirzaei, Shahnam ^a   Hosangadi, Anup ^a   Kastner, Ryan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMON SUBEXPRESSION ELIMINATION ALGORITHM; COMPUTER DESIGNS; DISTRIBUTED ARITHMETIC; DYNAMIC POWER CONSUMPTION; EMBEDDED MULTIPLIERS; FINITE IMPULSE RESPONSE FILTERS; FPGA IMPLEMENTATIONS; HIGH SPEEDS; INTERNATIONAL CONFERENCES; PARALLEL IMPLEMENTATIONS; XILINX VIRTEX;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMPULSE RESPONSE; SPEED; WAVE FILTERS;

FIR FILTERS;

EID: 49749090125     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380833     Document Type: Conference Paper

References (22)

1. K.D.Underwood and K.S.Hemmert, "Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance," presented at International Symposium on Field-Programmable Custom Computing Machines, California, USA, 2004.
2. L.Zhuo and V.K.Prasanna, "Sparse Matrix-Vector Multiplication on FPGAs," presented at International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, 2005.
3. Y.Meng, A.P.Brown, R.A.Iltis, T.Sherwood, H.Lee, and R.Kastner, "MP Core: Algorithm and Design Techniques for Efficient Channel Estimation in Wireless Applications," presented at Design Automation Conference (DAC), Anaheim, CA, 2005.
4. B. L. Hutchings and B. E. Nelson, "Gigaop DSP on FPGA," presented at Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001 IEEE International Conference on, 2001.
5. A.Alsolaim, J.Becker, M.Glesner, and J.Starzyk, "Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems," presented at International Symposium on Field Programmable Custom Computing Machines (FCCM), 2000.
6. S.J.Melnikoff, S.F.Quigley, and M.J.Russell, "Implementing a Simple Continuous Speech Recognition System on an FPGA," presented at International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2002.
7. T.Yokota, M.Nagafuchi, Y.Mekada, T.Yoshinaga, K.Ootsu, and T. Baba, "A Scalable FPGA-based Custom Computing Machine for Medical Image Processing," presented at International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2002.
8. K.Chapman, "Constant Coefficient Multipliers for the XC4000E," Xilinx Technical Report 1996.
9. K. Wiatr and E. Jamro, "Constant coefficient multiplication in FPGA structures," presented at Euromicro Conference, 2000. Proceedings of the 26th, 2000.
10. M. J. Wirthlin and B. McMurtrey, "Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures," presented at International Conference on Field Programmable Logic and Applications (FPL), 2001.
11. M. J.Wirthlin, "Constant Coefficient Multiplication Using Look-Up Tables," Journal of VLSI Signal Processing, vol. 36, pp. 7-15, 2004.
12. "Distributed Arithmetic FIR Filter v9.0," Xilinx Product Specification 2004.
13. T. Sasao, Y. Iguchi, and T. Suzuki, "On LUT Cascade Realizations of FIR Filters," presented at Euromicro Conference on Digital System Design (DSD), 2005.
14. G.R.Goslin, "A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific Digital Signal Processing Performance," Xilinx Application Note, San Jose 1995.
15. M.Potkonjak, M.B.Srivastava, and A.P.Chandrakasan, "Multiple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 1996.
16. R.I.Hartley, "Subexpression sharing in filters using canonic signed digit multipliers," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], vol. 43, pp. 677-688, 1996.
17. H.T.Nguyen and A.Chatterjee, "Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 8, pp. 419-424, 2000.
18. H.-J. Kang, H. Kim, and I.-C. Park, "FIR filter synthesis algorithms for minimizing the delay and the number of adders," presented at Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on, 2000.
19. A.Hosangadi, F.Fallah, and R.Kastner, "Reducing Hardware Compleity of Linear DSP Systems by Iteratively Eliminating Two Term Common Subexpressions," presented at Asia South Pacific Design Automation Conference, Shanghai, 2005.
20. M. Yamada and A. Nishihara, "High-speed FIR digital filter with CSD coefficients implemented on FPGA," presented at Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific, 2001.
21. H.Safiri, M.Ahmadi, G.A.Jullien, and W.C.Miller, "A new algorithm for the elimination of common subexpressions in hardware implementation of digital filters by using genetic programming," presented at Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on, 2000.
22. A.Hosangadi, F.Fallah, and R.Kastner, "Reducing Hardware complexity by iteratively eliminating two term common subexpressions," presented at Asia South Pacific Design Automation Conference (ASP-DAC), 2005.