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Volumn , Issue , 2006, Pages 253-256

Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; DIGITAL SIGNAL PROCESSORS; ENERGY DISSIPATION;

EID: 43749091973     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2006.270321     Document Type: Conference Paper
Times cited : (13)

References (18)
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  • 3
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    • Power-Aware Technology Mapping for LUT-Based FPGAs
    • Anderson, J., and Najm, F.N., Power-Aware Technology Mapping for LUT-Based FPGAs, in Proc. FPT 2002, pp. 211-218.
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  • 4
    • 0032627268 scopus 로고    scopus 로고
    • Power-Dissipation Driven FPGA Place and Route Under Timing Constraints
    • May
    • K. Roy, "Power-Dissipation Driven FPGA Place and Route Under Timing Constraints", in IEEE TCAS, vol. 46 no. 5, pp. 634-637, May 1999.
    • (1999) IEEE TCAS , vol.46 , Issue.5 , pp. 634-637
    • Roy, K.1
  • 5
    • 0031623054 scopus 로고    scopus 로고
    • High-performance Carry Chains for FPGAs
    • S. Hauck, M. Hosler, and T. Fry, "High-performance Carry Chains for FPGAs," in Proc. FPGA 1998, pp.223-233.
    • (1998) Proc. FPGA , pp. 223-233
    • Hauck, S.1    Hosler, M.2    Fry, T.3
  • 8
    • 0032597867 scopus 로고    scopus 로고
    • S.D. Haynes, A. Ferrari, and P.Y.K. Cheung, Flexible Reconfigurable Multiplier Blocks Suitable for Enhancing the Architecture of FPGAs, in Proc. CICC 1999, pp. 191-194.
    • S.D. Haynes, A. Ferrari, and P.Y.K. Cheung, "Flexible Reconfigurable Multiplier Blocks Suitable for Enhancing the Architecture of FPGAs," in Proc. CICC 1999, pp. 191-194.
  • 10
    • 30544455212 scopus 로고    scopus 로고
    • A Detailed Power Model for Field-Programmable Gate Arrays
    • Apr
    • KXW, Poon and S.J.E Wilton, "A Detailed Power Model for Field-Programmable Gate Arrays" in ACM TODAES vol. 10 issue 2, pp.279-302, Apr. 2005.
    • (2005) ACM TODAES , vol.10 , Issue.2 , pp. 279-302
    • KXW, P.1    Wilton, S.J.E.2
  • 11
    • 0028711580 scopus 로고
    • A Survey of Power Estimation Techniques in VLSI Circuits
    • F.N. Najm, "A Survey of Power Estimation Techniques in VLSI Circuits," IEEE VLSI, vol. 2, no. 4, pp. 446-455, 1994.
    • (1994) IEEE VLSI , vol.2 , Issue.4 , pp. 446-455
    • Najm, F.N.1
  • 13
    • 0030165662 scopus 로고    scopus 로고
    • Information Theoretic Measures for Power Analysis
    • Jun
    • D. Marculescu, R. Marculescu, M. Pedram, "Information Theoretic Measures for Power Analysis," in IEEE TCAD, vol. 15 no. 6, pp. 599-610, Jun 1996.
    • (1996) IEEE TCAD , vol.15 , Issue.6 , pp. 599-610
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  • 14
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    • Architectural Power Analysis: The Dual Bit Type Method
    • June
    • P.E. Landman and J.M. Rabaey, "Architectural Power Analysis: The Dual Bit Type Method," in IEEE TVLSI. Vol. 3 No. 2, pp. 173-187, June 1995.
    • (1995) IEEE TVLSI , vol.3 , Issue.2 , pp. 173-187
    • Landman, P.E.1    Rabaey, J.M.2
  • 15
    • 46249100189 scopus 로고    scopus 로고
    • Activity Estimation For Field Programmable Gate Arrays
    • To appear in
    • J. Lamoureux, S.J.E. Wilton, "Activity Estimation For Field Programmable Gate Arrays," To appear in FPL 2006.
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    • Lamoureux, J.1    Wilton, S.J.E.2
  • 16
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  • 17
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    • A verilog RTL synthesis tool for heterogeneous FPGAs
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  • 18
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    • SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications
    • to appear in
    • E. Senn, J. Laurent, N. Julien, E. Martin, "SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications," to appear in EURASIP.
    • EURASIP
    • Senn, E.1    Laurent, J.2    Julien, N.3    Martin, E.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.