PSP: An advanced surface-potential-based MOSFET model

Transistor Level Modeling For Analog/RF IC Design

Volumn , Issue , 2006, Pages 29-66

  Van Langevelde, R ^a   Gildenblat, G ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b The Pennsylvania State University   (United States)

Author keywords

compact model; JUNCAP2; MOSFET; PSP; Surface potential

Indexed keywords

EID: 77949895927     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/1-4020-4556-5_2     Document Type: Chapter

References (73)

1. BSIM3 and BSIM4: www-device.eecs.berkeley.edu
2. Velghe, R. M. D. A.; Klaassen, D. B. M.; Klaassen, F. M. "MOS Model 9", NL-UR 003/94, Philips Electron. N. V., 1994. internet: www.semiconductors.philips.com/PhilipsModels.
3. Watts, J.; et al. "Advanced compact models for MOSFETs", In Proc. NSTI-Nanotech, 2005, 3-12
4. Gildenblat, G.; Wang, H.; Chen, T.-L.; Gu, X.; Cai, X. "SP: An advanced surfacepotentialbased compact MOSFET model", IEEE J. Solid-State Circ., 2004, 39, 1394-1406.
5. Chen, T.-L.; Gildenblat, G. "Analytical approximation for the MOSFET surface potential", Solid-State Electron., 2001, 45, 335-339.
6. Chen, T. L.; Gildenblat, G. "Symmetric bulk charge linearisation in charge-sheet MOSFET model", Electron. Lett., 2001, 37, 791-793.
7. Gildenblat, G.; Chen, T.-L. "Overviewof an advanced surface-potential-based model (SP) ", In Proc. NSTI-Nanotech, 2002, 657-661.
8. Wang, H.; Chen, T.-L.; Gildenblat, G. "Quasi-static and nonquasi-static compact MOSFET models based on symmetric linearization of the bulk and inversion charges", IEEE Trans. Electron Dev., 2003, 50, 2262-2272.
9. Gu, X.; Wang, H.; Chen, T. L.; Gildenblat, G. "Substrate current in surface-potentialbased models", In Proc. NSTI-Nanotech, 2003, 310-312.
10. Gildenblat, G.; Chen, T.-L.; Gu, X.; Wang, H.; Cai, X. "SP: An advanced surfacepotentialbased compact MOSFET model", In Proc. CICC, 2003, 233-240.
11. Gildenblat, G.; Cai, X.; Chen, T.-L.; Gu, X.; Wang, H. "Reemergence of the surfacepotentialbased compact MOSFET models", In IEDM Tech. Digest, 2003, 863-866
12. Gu, X.; Chen, T.-L.; Gildenblat, G.; Workman, G. O.; Veeraraghavan, S.; Shapira, S.; Stiles, K. "A surface potential-based compact model of n-MOSFET gate-tunneling current", IEEE Trans. Electron Dev., 2004, 51, 127-135.
13. Gildenblat, G.; McAndrew, C. C.; Wang, H.; Wu, W.; Foty, D.; Lemaitre, L.; Bendix, P. "Advanced compact models: Gateway to modern CMOS design", In Proc. ICECS, 2004, 638-641.
14. Wu, W.; Chen, T.-L.; Gildenblat, G.; McAndrew, C. C. "Physics-based mathematical conditioning of the MOSFET surface potential equation", IEEE Transactions on Electron Dev., July 2004, 51, 1196-1200.
15. Wang, H.; Gildenblat, G. "A robust large signal non-quasi-static MOSFET model for circuit simulation", In Proc. IEEE CICC, 2004, 5-8.
16. Chen, T.-L.; Gildenblat, G. "An extended analytical approximation for the MOSFET surface potential", Solid-State Electron., 2005, 49, 267-270.
17. Wu, W.; et al., "SP-SOI: A third generation surface potential based compact SOI MOSFET model", In Proc. IEEE CICC, 2005, 819-822.
18. van Langevelde, R.; Klaassen, F. M. "An explicit surface-potential-based MOSFET model for circuit simulation", Solid-State Electron., 2000, 44, 409-418.
19. van Langevelde, R.; Tiemeijer, L. F.; Havens, R. J.; Knitel, M. J.; Roes, R. F. M.; Woerlee, P. H.; Klaassen, D. B. M. "RF-distortion in deep-submicron CMOS technologies", In IEDM Tech. Digest, 2000, 807-810.
20. van Langevelde, R.; Scholten, A. J.; Havens, R. J.; Tiemeijer, L. F.; Klaassen, D. B. M. "Advanced compact MOS modeling", In Proc. ESSDERC, 2001, 81-88.
21. van Langevelde, R.; Scholten, A. J.; Duffy, R.; Cubaynes, F. N.; Knitel, M. J.; Klaassen, D. B. M. "Gate current: Modeling, -L extraction and impact on RF performance", In IEDM Tech. Digest, 2001, 289-292.
22. van Langevelde, R.; Scholten, A. J.; Klaassen, D. B. M. "MOS Model 11, level 1101", NL-UR 2002/802, Philips Electron. N. V., 2002. www.semiconductors.philips.com/PhilipsModels/mosmodels/model11
23. van Langevelde, R.; Scholten, A. J.; Klaassen, D. B. M. "Physical background of MOS Model 11, level 1101", NL-UR 2003/00238, Philips Electron. N. V., 2003. www.semiconductors.philips.com/PhilipsModels/mosmodels/ model11
24. van Langevelde, R.; Paasschens, J. C. J.; Scholten, A. J.; Havens, R. J.; Tiemeijer, L. F.; Klaassen, D. B. M. "New compact model for induced gate current noise", In IEDM Tech. Digest, 2003, 867-870.
25. van Langevelde, R.; Scholten, A. J.; Klaassen, D. B. M. "Recent enhancements of MOS model 11", In Proc. NSTI-Nanotech, 2004, 60-65.
26. Klaassen, D. B. M.; van Langevelde, R.; Scholten, A. J. "Compact CMOS modeling for advanced analog and RF applications", IEICE Trans. Electron., 2004, E87-C, 854-866.
27. Pao, H. C.; Sah, C. T. "Effects of diffusion current on characteristics of metal-oxide (Insulator)-semiconductor transistors", Solid-State Electron., 1966, 9, 927-937.
28. Brews, J. R. "A charge-sheet model of the MOSFET", Solid-State Electron., 1978, 21, 345-355.
29. Tsividis, Y. P. Operation and modeling of the MOS transistor, New York: McGraw-Hill, 1999.
30. Scholten, A. J.; Smit, G. D. J.; Durand, M.; van Langevelde, R.; Dachs, C. J. J.; Klaassen, D. B. M. "A new compact model for junctions in advanced CMOS technologies", In IEDM Tech. Digest, 2005, 209-212.
31. Wang, H. et al. "Unified non-quasi-static MOSFET model for large-signal and smallsignal simulations", In Proc. IEEE CICC, 2005, 823-826.
32. PSP: pspmodel.ee.psu.edu
33. Arora, N. D. MOSFET models for VLSI circuit simulation, Wien: Springer-Verlag, 1993.
34. McAndrew, C. C.; Victory, J. J. "Accuracy of approximations in MOSFET charge models", IEEE Trans. Electron Dev., 2002, 49, 72-81.
35. Sah, C. T. "Ahistory of MOStransistor compact modeling", In Proc. NSTI-Nanotech, 2005, 437-390.
36. Boothroyd, A. R.; Tarasewicz, S. W.; Slaby, C. "MISNAN-Aphysically based continuous MOSFET model for CAD applications", IEEE Trans. Comput.-Aided Design, 1991, 10, 1512-1529.
37. Rios, R.; Murdanai, S.; Shih W.-K.; Packan, P. "An efficient surface potential solution algorithm for compact MOSFET models", In IEDM Tech. Digest, 2004, 755-758.
38. Miura-Mattausch, M. et al. "HiSIM: A MOSFET model for circuit simulation connecting circuit performance with technology", In IEDMTech. Digest, 2002, 109-112.
39. Turchetti, C.; Masetti, G. "A CAD-oriented analytical MOSFET model for highaccuracy applications", IEEE Trans. Comput.-Aided Design, 1984, 3, 117-122.
40. Bagheri, M.; Tsividis, Y. "A small-signal DC-to-high-frequency non-quasistatic model for four-terminal MOSFETs valid in all regions of operation", IEEE Trans. on Electron Dev., 1985, 32, 2383-91.
41. Howes, R. et al. "A charge-conserving silicon-on-sapphire SPICE MOSFET model for analog design", IEEE Int. Symp. Circ. Systems, 1991, 4, 2160-2163.
42. Nguyen, T. N.; Plummer, J. D. "Physical mechanisms responsible for short channel effects in MOS devices", In IEDM Tech. Digest, 1981, 596-599.
43. Skotnicki, T.; Merckel, G.; Pedron, T. "The voltage-doping transformation: A new approach to modeling of MOSFET short-channel effects", IEEE Electron Dev. Lett., 1988, 9, 109-112.
44. Miura-Mattausch, M. "Analytical MOSFET model for quarter micron technologies", IEEE Trans. Comput.-Aided Design, 1994, 13, 610-615.
45. Joardar, K.; Gullapulli, K. K.; McAndrew, C. C.; Burnham M. E.; Wild, A. "An improved MOSFET model for circuit simulation", IEEE Trans. Electron Dev., 1998, 45, 134-148.
46. Van de Wiele, F. "A long-channel MOSFET model", Solid-State Electron., 1979, 22, 991-987.
47. Huang, C.-L.; Arora, N. "Characterization and modeling of the n- and p-Channel MOSFETs inversion-layer mobility in the range 25-125°C", Solid-State Electron., 1994, 37, 97-103.
48. Bendix, P.; Rakers, P.; Wagh, P.; Lemaitre, L.; Grabinski, W.; McAndrew, C. C.; Gu, X.; Gildenblat, G. "RF distortion analysis with compact MOSFET models", In Proc. IEEE CICC, 2004, 9-12.
49. Scharfetter; D. L.; Gummel, H. K. "Large-signal analysis of a silicon read diode oscillator", IEEE Trans. Electron Dev., 1969, 16, 64-77.
50. El-Mansy, Y. A.; Boothroyd, A. R. "Asimple two-dimensional model for IGFET operation in the saturation region", IEEE Trans. Electron Dev., 1977, 24, 254-262.
51. Cao, K. M. et al. "Modeling of pocket implanted MOSFETs for anomalous analog behavior", In IEDM Tech. Digest, 1999, 171-174.
52. Ward, D. E.; Dutton, R. W. "A charge-oriented model for MOS transistor capacitances", IEEE J. Solid-State Circ., 1978, 13, 703-708.
53. Foty, D. MOSFET Modeling with SPICE: Principles and Practice, Upper Saddle River, NJ: Prentice-hall, 1997.
54. Liu, W. MOSFET Models for SPICE Simulations Including BSIM3v3, BSIM4, New York: Wiley, 2001.
55. Victory, J.; Yan, Z.; Gildenblat, G.; McAndrew, C.; Zheng, J. "A physically based scalable varactor model and extractor methodology for RF applications", IEEE Trans. Electron Dev., 2005, 52, 1343-1353.
56. Chen, J.; Chan, T. Y.; Ko, P. K.; Hu, C. "Subbreakdown drain leakage current in MOSFET", IEEE Electron Dev. Lett., 1987, 8, 515-517.
57. Kane, E. O. "Zener tunneling in semiconductors", J. Phys. Chem. Solids, 1959, 12, 181-188.
58. JUNCAP level 1: www.semiconductors.philips.com/PhilipsModels
59. Hurkx, G. A. M.; de Graaff, H. C.; Kloosterman, W. J.; Knuvers, M. P. G. "A new analytical diode model including tunneling and avalanche breakdown", IEEE Trans. Electron Dev., 1992, 39, 2090-2098.
60. Wright, P. J.; Saraswat, K. C. "Thickness limitations of SiO2 gate dielectrics for MOS ULSI", IEEE Trans. Electron Dev., 1990, 37, 1884-1892.
61. Choi, C.-H.; Nam, K.-Y.; Yu, Z.; Dutton, R. W. "Impact of gate direct tunneling current on circuit performance: A simulation study", IEEE Trans. Electron Dev., 2001, 48, 2823-2829.
62. Tsu, R.; Esaki, L. "Tunneling in a finite superlattice", Appl. Phys. Lett., 1973, 22, 562-564.
63. Scholten, A. J.; Tiemeijer, L. F.; van Langevelde, R.; Havens, R. J.; Zegers-van Duijnhoven, A. T. A.; Venezia, V. C. "Noise modeling for RF CMOS circuit simulation", IEEE Trans. Electron Dev., 2003, 50, 618-632.
64. Hung, K. K.; Ko, P. K.; Hu, C.; Cheng, Y. C. "A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors", IEEE Trans. Electron Dev., 1990, 37, 654-665.
65. Hung, K. K.; Ko, P. K.; Hu, C.; Cheng, Y. C. "A physics-based MOSFET noise model for circuit simulators", IEEE Trans. Electron Dev., 1990, 37, 1323-1333.
66. van der Ziel, A. Noise Solid-State Dev. Circuits, New York: Wiley-Interscience, 1986.
67. Klaassen, F. M.; Prins, J. "Thermal noise of MOS transistors", Philips Res. Reports, 1967, 22, 505-514.
68. Klaassen, F. M. "Comments on hot carrier noise in field-effect transistors", IEEE Trans. Electron Dev., 1971, 18, 74-75.
69. Paasschens, J. C. J.; Scholten, A. J.; van Langevelde, R. "Generalisations of the Klaassen-Prins equation for calculating the noise of semiconductor Devices", IEEE Trans. Electron Dev., 2005, 52, 2463-2472.
70. Scholten, A. J.; Tiemeijer, L. F.; de Vreede, P. W. H.; Klaassen, D. B. M. "A large signal non-quasi-static MOS model for RF circuit simulation", In IEDM Tech. Digest, 1999, 163-166.
71. Mancini, P.; Turchetti, C.; Masetti, G. "A non-quasi-static analysis of the transient behavior of the long-channel MOSFETvalid in all regions of operation", IEEE Trans. Electron Dev., 1987, ED-34, 325-334.
72. Hwang, S. W.; Yoon, T.-W.; Kwon, D. H.; Kim, K. H. "A physics-based SPICEcompatible non-quasi-static MOS transient model for RF circuit simulation", Jpn. J. Appl. Phys., 1998, 37, L119-L121.
73. CMC-website: www.eigroup.org/cm