Steep subthreshold slope n- and p-type Tunnel-FET devices for low-power and energy-efficient digital circuits

IEEE Transactions on Electron Devices

Volumn 56, Issue 11, 2009, Pages 2752-2761

  Khatami, Yasin ^a   Banerjee, Kaustav ^a  

^a Santa Barbara   (United States)

Author keywords

Band to band (B2B) tunneling; Energy efficient device; Low power (LP); Sub kT q device; Subthreshold swing; Tunnel field effect transistor (T FET)

Indexed keywords

BAND-TO-BAND (B2B) TUNNELING; ENERGY-EFFICIENT DEVICE; LOW POWER (LP); SUB-KT/Q DEVICE; SUBTHRESHOLD SWING;

DIGITAL DEVICES; DIGITAL INTEGRATED CIRCUITS; ENERGY EFFICIENCY; GATES (TRANSISTOR); MESFET DEVICES; NONVOLATILE STORAGE; SOLID-STATE SENSORS; THRESHOLD VOLTAGE; TUNNELING (EXCAVATION); TUNNELS; WIND TUNNELS;

FIELD EFFECT TRANSISTORS;

EID: 70350705816     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2030831     Document Type: Article

References (37)

1. H. F. Dadgour, S. C. Lin, and K. Banerjee, "A statistical framework for estimation of full-chip leakage power distribution under parameter variations," IEEE Trans. Electron Devices, vol. 54, no. 11, pp. 2930-2945, Nov. 2007.
2. K. Banerjee, S.-C. Lin, A. Keshavarzi, S. Narendra, and V. De, "A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management," in IEDM Tech. Dig., 2003, pp. 887-890.
3. D. J. Wouters, J. P. Colinge, and H. E. Maes, "Subthreshold slope in thin-film SOI MOSFETs," IEEE Trans. Electron Devices, vol. 37, no. 9, pp. 2022-2033, Sep. 1990.
4. H. C. Lin, M. H. Lee, C. J. Su, and S. W. Shen, "Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2471-2477, Oct. 2006.
5. K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, "I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q," in IEDM Tech. Dig., 2002, pp. 289-292.
6. J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, "Band-to-band tunneling in carbon nanotube field-effect transistors," Phys. Rev. Lett., vol. 93, no. 19, pp. 196 805-1-196 805-4, Nov. 2004.
7. J. Knoch, S. Mantl, and J. Appenzeller, "Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices," Solid State Electron., vol. 51, no. 4, pp. 572-578, Apr. 2007.
8. J. Koga and A. Toriumi, "Three-terminal silicon surface junction tunneling device for room temperature operation," IEEE Electron Device Lett., vol. 20, no. 10, pp. 529-531, Oct. 1999.
9. Q. Zhang, W. Zhao, and A. Seabaugh, "Low-subthreshold-swing tunnel transistors," IEEE Electron Device Lett., vol. 27, no. 4, pp. 297-300, Apr. 2006.
10. C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, and S. Deleonibus, "Lateral interband tunneling transistor in silicon-on-insulator," Appl. Phys. Lett., vol. 84, no. 10, pp. 1780-1782, Mar. 2004.
11. W. M. Reddick and G. A. J. Amaratunga, "Silicon surface tunnel transistor," Appl. Phys. Lett., vol. 67, no. 4, pp. 494-496, Jul. 1995.
12. K. K. Bhuwalka, J. Schulze, and I. Eisele, "Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering," IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 909-917, May 2005.
13. K. Boucart and A. Ionescu, "Double gate tunnel FET with high-k gate dielectric," IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725-1733, Jul. 2007.
14. K. Boucart and A. M. Ionescu, "Length scaling of the double gate tunnel FET with a high-k gate dielectric," Solid State Electron., vol. 51, no. 11/12, pp. 1500-1507, Nov./Dec. 2007.
15. P. F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch, "Complementary tunneling transistor for low power application," Solid State Electron., vol. 48, no. 12, pp. 2281-2286, Dec. 2004.
16. K. K. Bhuwalka, S. Sedlmaier, A. K. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele, "Vertical tunnel field-effect transistor," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 279-282, Feb. 2004.
17. K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima, and I. Eisele, "P-channel tunnel field-effect transistors down to sub-50 nm channel lengths," Jpn. J. Appl. Phys., vol. 45, no. 4B, pp. 3106-3109, Apr. 2006.
18. W. Hansch, P. Borthen, J. Schulze, C. Fink, T. Sulima, and I. Eisele, "Performance improvement in vertical surface tunneling transistors by a Boron surface phase," Jpn. J. Appl. Phys., vol. 40, no. 5A, pp. 3131-3136, May 2001.
19. W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, Aug. 2007.
20. Q. Zhang, S. Sutar, T. Kosel, and A. Seabaugh, "Fully-depleted Ge interband tunnel transistor: Modeling and junction formation," Solid State Electron., vol. 53, no. 1, pp. 30-35, Jan. 2009.
21. T. Nirschl, M. Weis, M. Fulde, and D. Schmitt-Landsiedel, "Revision of tunneling field effect transistor in standard CMOS technologies," IEEE Trans. Electron Devices, vol. 28, no. 4, p. 315, Apr. 2007.
22. E.-H. Toh, G. H. Wang, L. Chan, D. Sylvester, C.-H. Heng, G. Samudra, and Y.-C. Yeo, "Device design and scalability of a double-gate tunneling field-effect transistor with silicon-germanium source," Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2593-2597, Apr. 2008.
23. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS) 2007. [Online]. Available: http:// www.itrs.net
24. L. Esaki, "New phenomenon in narrow Germanium p-n junctions," Phys. Rev., vol. 109, no. 2, pp. 603-604, Jan. 1958.
25. T. Baba, "Proposal for surface tunnel transistors," Jpn. J. Appl. Phys., vol. 31, no. 4B, pp. L455-L557, Apr. 1992.
26. L. D. Landau and E. M. Lifshitz, Quantum Mechanics. Reading, MA: Addison-Wesley, 1990, p. 174.
27. S. M. Sze, Physics of Semiconductor Devices, 3rd ed. New York: Wiley, 1998.
28. K. Kim and Y. H. Lee, "Temperature-dependent critical layer thickness for strained-layer heterostructures," Appl. Phys. Lett., vol. 67, no. 15, pp. 2212-2214, Oct. 1995.
29. B. S. Meyerson, "UHV/CVD growth of Si and SiGe alloys: Chemistry, physics and device applications," Proc. IEEE, vol. 80, no. 10, pp. 1592-1608, Oct. 1992.
30. x films from hydrides," J. Appl. Phys., vol. 69, no. 6, pp. 3729-3732, Mar. 1991.
31. Taurus MEDICI User's Manual, Synopsys, Mountain View, CA, ver. 2007.3, 2007.
32. L. Yang, J. R. Watling, R. C. W. Wilkins, M. Borici, J. R. Barker, A. Asenov, and S. Roy, "Si/SiGe heterostructure parameters for device simulations," Semicond. Sci. Technol., vol. 19, no. 10, pp. 1174-1182, Oct. 2004.
33. G. Wilk, R. Wallace, and J. Anthony, "High-k gate dielectrics: Current status and materials properties considerations," J. Appl. Phys., vol. 89, no. 10, pp. 5243-5275, May 2001.
34. K. K. Bhuwalka, J. Schulze, and I. Eisele, "A simulation approach to optimize the electrical parameters of a vertical tunnel FET," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1541-1547, Jul. 2005.
35. E. O. Kane, "Zener tunneling in semiconductors," J. Phys. Chem. Solids, vol. 12, no. 2, pp. 181-188, Jan. 1960.
36. Predictive Technology Model. [Online]. Available: http://www.eas.asu.edu/ ~ptm/
37. R. Woo, H.-Y. S. Koh, C. Onal, P. B. Griffin, and J. D. Plummer, "BTBT transistor scaling: Can they be competitive with MOSFETs?" in Proc. Device Res. Conf. Tech. Dig., 2008, pp. 75-76.