A statistical framework for estimation of full-chip leakage-power distribution under parameter variations

IEEE Transactions on Electron Devices

Volumn 54, Issue 11, 2007, Pages 2930-2945

  Dadgour, Hamed F ^a   Lin, Sheng Chih ^a   Banerjee, Kaustav ^a  

^a University of California   (United States)

Author keywords

CMOS devices; Leakage currents; Parameter variations; Power dissipation; Temperature variations; Within die variations; Yield estimation

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC CIRCUITS; PARAMETER ESTIMATION; TEMPERATURE DISTRIBUTION; THRESHOLD VOLTAGE; TRANSISTORS;

LEAKAGE DISTRIBUTION; PARAMETER VARIATIONS; STACKING EFFECT;

CHIP SCALE PACKAGES;

EID: 36248933153     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.906960     Document Type: Article

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