A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal Management

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 887-890

  Banerjee, Kaustav ^a   Lin, Sheng Chih ^a   Keshavarzi, Ali ^b   Narendra, Siva ^b   De, Vivek ^b  

^a University of California   (United States)

^b INTEL RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROTHERMAL EFFECTS; SEMICONDUCTOR SCALING; THERMAL MANAGEMENT;

CHIP SCALE PACKAGES; CMOS INTEGRATED CIRCUITS; COOLING; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; FREQUENCY RESPONSE; LEAKAGE CURRENTS; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; NANOSTRUCTURED MATERIALS; PYROLYSIS; SEMICONDUCTING SILICON; TEMPERATURE DISTRIBUTION; THERMAL EFFECTS; VOLTAGE MEASUREMENT;

SEMICONDUCTOR JUNCTIONS;

EID: 0842288145     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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