Process variation aware thread mapping for chip multiprocessors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 821-826

  Hong, S ^a   Narayanan, S H K ^a   Kandemir, M ^a   Ozturk O ^b  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b BILKENT UNIVERSITY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; MANUFACTURE; MAPPING; MULTIPROCESSING SYSTEMS;

ALTERNATE APPROACHES; CHIP MULTI-PROCESSORS (CMPS); CHIP MULTIPROCESSOR; COMPUTATIONAL CAPABILITY; EXPERIMENTAL EVIDENCE; MANUFACTURING TECHNOLOGIES; OVERALL EXECUTION; PROCESS VARIATION;

INTEGRATED CIRCUIT DESIGN;

EID: 70350045024     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090776     Document Type: Conference Paper

References (30)

1. http://techresearch.intel.com/articles/Tera-Scale/1449.htm.
2. http://www.amd.com/us-en/Processors/ProductInformation/.
3. http://www.intel.com/pressroom/kits/itanium2/.
4. http://www.intel.com/products/processor/xeon5000/.
5. http://www.research.ibm.com/cell/.
6. An Overview of UltraSPARC TM III Cu UltraSPARC III Moves to Copper Technology Version 1.1, 2003.
7. OpenMP Application Program Interface Version 2.5 Public Draft, 2004.
8. Simics User Guide for Unix 2.2.12, 2005.
9. A. Agarwal, et al., "A process-tolerant cache architecture for improved yield in nanoscale technologies," TVLSI, vol. 13, no. 1, pp. 27-38, Jan. 2005.
10. V. Agarwal, et al., "Clock rate versus ipc: the end of the road for conventional microarchitectures," in ISCA, 2000, pp. 248-259.
11. D. Animesh, et al., "Speed binning aware design methodology to improve profit under parameter variations," ASPDAC, pp. 6 pp.-, 24-27 Jan. 2006.
12. S. Borkar, et al., "Parameter variations and impact on circuits and microarchitecture," DAC, pp. 338-342, 2-6 June 2003.
13. K. Bowman, et al., "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," Solid-State Circuits, IEEE Journal of, vol. 37, no. 2, pp. 183-190, Feb 2002.
14. K. Bowman, et al., "Maximum clock frequency distribution model with practical vlsi design considerations," ICICDT, pp. 183-191, 2004.
15. K. A. Bowman, et al., "Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors," in ISLPED, 2007, pp. 50-55.
16. S. M. Burns,et al. "Comparative analysis of conventional and statistical design techniques," in DAC, 2007, pp. 238-243.
17. Y. Cao and L. T. Clark, "Mapping statistical process variations toward circuit performance variability: an analytical modeling approach," in DAC, 2005, pp. 658-663.
18. L. Chun, et al., "Exploiting barriers to optimize power consumption of cmps," IPDPS, pp. 5a-5a, 04-08 April 2005.
19. J. Donald and M. Martonosi, "Power efficiency for variation-tolerant multicore processors," in ISLPED, 2006, pp. 304-309.
20. A. Jaleel, et al., "Last level cache (llc) performance of data mining workloads on a cmp - a case study of parallel bioinformatics workloads," HPCA, pp. 88-98, 11-15 Feb. 2006.
21. H. Jin, et al., The OpenMP Implementation of NAS Parallel Benchmarks and Its Performance, October 1999.
22. M. Ke and J. Russ, "Process variation aware cache leakage management," ISLPED, pp. 262-267, 4-6 Oct. 2006.
23. P. Kongetira, et al., "Niagara: A 32-way multithreaded sparc processor," IEEE Micro, vol. 25, no. 2, pp. 21-29, 2005.
24. H. Masuda, et al., "Challenge: variability characterization and modeling for 65- to 90-nm processes," Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005, pp. 593-599, 18-21 Sept. 2005.
25. Y. Matsumoto, et al., "Performance and yield enhancement of fpgas with within-die variation using multiple configurations," in FPGA, 2007, pp. 169-177.
26. S. Nassif, "Modeling and analysis of manufacturing variations," Custom Integrated Circuits, 2001, IEEE Conference on., pp. 223-228, 2001.
27. B. Nayfeh and K. Olukotun, "A single-chip multiprocessor," Computer, vol. 30, no. 9, pp. 79-85, Sep 1997.
28. O. Ozturk, et al., "Compiler-directed variable latency aware spm management to cope with timing problems," in CGO, 2007, pp. 232-243.
29. S. Samaan, "The impact of device parameter variations on the frequency and performance of vlsi chips," ICCAD, pp. 343-346, 7-11 Nov. 2004.
30. S. Srinivasan, et al., "Process variation aware parallelization strategies for mpsocs," SOCC, pp. 179-182, Sept. 2006.