Maximum clock frequency distribution model with practical VLSI design considerations

2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2004, Pages 183-191

  Bowman, Keith A ^a   Samaan, Samie B ^a   Hakim, Nagib Z ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABERRATIONS; CLOCKS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; FREQUENCIES; INTEGRATED CIRCUIT MANUFACTURE; LENSES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; PARAMETER ESTIMATION; PROCESS CONTROL; VECTORS;

CRITICAL DIMENSIONS (CD); FREQUENCY DISTRIBUTIONS; RETURN ON INVESTMENT (ROI); WITHIN DIE (WID) PARAMETERS;

VLSI CIRCUITS;

EID: 4143127818     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

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