The impact of device parameter variations on the frequency and performance of VLSI chips

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 343-346

  Samaan, Samie B ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; PARAMETER ESTIMATION; STATISTICAL PROCESS CONTROL; TEMPERATURE DISTRIBUTION; THERMAL EFFECTS; TRANSISTORS; VLSI CIRCUITS;

PROCESS GENERATION; RANDOM VARIATION; TEMPERATURE GRADIENTS; WITHIN-DIE (WID);

MICROPROCESSOR CHIPS;

EID: 16244383198     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. P. Stolk, et al, "Modeling Statistical Dopant Fluctuations in MOS Transistors", IEEE Trans. on Electron Devices, Vol. 45, No. 9, Sept. 1998.
2. Hane, M., Ikezawa, T., Ezaki, T., "Coupled atomistic 3D process/device simulation considering both line-edge roughness and random-discrete-dopant effects", International Conference on the Simulation of Semiconductor Processes and Devices. SISPAD 2003, 3-5 Sept.
3. International Technology Roadmap for Semiconductors (ITRS), 2001, '02 update, & 2003.
4. K. Bowman, S. Duvall, J. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on Maximum Clock Frequency Distribution for Giga-scale Integration", IEEE J. Solid State Circuits, Feb. 2002.
5. K. Bowman, S. Samaan, N. Hakim, "Maximum Clock Frequency Distribution Model with Practical VLSI Design Considerations", ICICDT, 2004.
6. Samie B. Samaan, "The Impact of Device Parameter Variations on the Frequency and Performance of Microprocessor Circuits", IEEE ISSCC Microprocessor Circuit Design Forum: Managing Variability on Sub-100nm Designs, Feb. 2004.
7. A. Srivastava et al, "Modeling and Analysis of Leakage Power Considering Within-Die Process Variations", ISLPED 2002, CA, USA.