Process variation aware parallelization strategies for MPSoCs

2006 IEEE International Systems-on-Chip Conference, SOC

Volumn , Issue , 2006, Pages 179-182

  Srinivasan, Suresh ^a   Ramadoss, Raghavan ^a   Vijaykrishnan, N ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; LOGIC DESIGN; NATURAL FREQUENCIES; PARALLEL PROCESSING SYSTEMS;

MULTIPROCESSOR SYSTEM ON CHIPS (MPSOC); PROCESSORS CORES;

MICROPROCESSOR CHIPS;

EID: 43749090216     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2006.283876     Document Type: Conference Paper

References (7)

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3. D. Blaaw and K. Chopra "CAD Tools for Variation Tolerence" Proceedings of Design Automation Conference (DAC), pg 766, 2005.
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6. M. Loghi, F, Anglollni, D. Bertozzl, L. Beninl and R. Zaffalon. "Analyzing On-Chip Communication in a MPSoC". In proceedings of Design Automation and Test in Europe, pg 752-757, DATE-2004.
7. D. Culler, J. P. Singh, and A. Gupta. "Parallel Computer Architecture: A Hardware/Software Approach" Morgan Kaufmann Publishers, 1998