A single-chip multiprocessor

Computer

Volumn 30, Issue 9, 1997, Pages 79-85

  Hammond, Lance ^a   Nayfeh, Basem A ^a,b   Olukotun, Kunle ^a,c,d,e  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSITY OF CINCINNATI   (United States)

^c CALVIN COLLEGE   (United States)

^d UNIVERSITY OF MICHIGAN   (United States)

^e IEEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; MULTIPROCESSING SYSTEMS; PROGRAM COMPILERS; TRANSISTORS;

SINGLE CHIP MULTIPROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0031235242     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/2.612253     Document Type: Article

References (10)

1. Y. Patt, "First Let's Get the Uniprocessor Right," Microprocessor Report, Aug. 5, 1996, pp. 23-24.
2. M. Hall et al., "Maximizing Multiprocessor Performance with the SUIF Compiler," Computer, Dec. 1996, pp. 84-88.
3. D. Tullsen, S. Eggers, and H. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," Proc. 22nd Ann. Int'l Symp. Computer Architecture, ACM Press, New York, 1995, pp. 392-403.
4. K. Olukotun et al., "The Case for a Single Chip Multiprocessor," Proc. 7th Int'l Conf. Architectural Support for Programming Languages and Operating Systems, ACM Press, New York, 1996, pp. 2-11.
5. G. Sohi, S. Breach, and T. Vijaykumar, "Multiscalar Processors," Proc. 22nd Ann. Int'l Symp. Computer Architecture, ACM Press, New York, 1995, pp. 414-425.
6. J. Oplinger et al., Software and Hardware for Exploiting Speculative Parallelism in Multiprocessors, Tech. Report CSL-TR-97-715, Computer Systems Laboratory, Stanford Univ., Stanford, Calif., 1997.
7. L. Gwennap, "Digital 21264 Sets New Standard," Microprocessor Report, Oct. 28, 1996, pp. 11-16.
8. J.L. Hennessy and D.A. Patterson, Computer Architecture A Quantitative Approach, 2nd Edition, Morgan Kaufman, San Francisco, 1996.
9. D.W. Wall, Limits of Instruction-Level Parallelism, WRL Research Report 93/6, Digital Western Research Laboratory, Palo Alto, Calif., 1993.
10. K. Yeager, "The MIPS R10000 Superscalar Microprocessor," IEEE Micro, Apr. 1996, pp. 28-40.