Exploiting barriers to optimize power consumption of CMPs

Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005

Volumn 2005, Issue , 2005, Pages

  Liu, Chun ^a   Sivasubramaniam, Anand ^a   Kandemir, Mahmut ^a   Irwin, Mary Jane ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-MULTIPROCESSORS (CMP); HARDWARE-SOFTWARE MECHANISM; SPECOMP SUITE; TRANSISTOR DESIGNS;

COMPUTER AIDED DESIGN; COMPUTER SYSTEMS; INTEGRATED CIRCUITS; PERFORMANCE; SIMULATORS; SYNCHRONIZATION;

ELECTRIC POWER UTILIZATION;

EID: 33746317769     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2005.211     Document Type: Conference Paper

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