Process variation aware cache leakage management

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 262-267

  Meng, Ke ^a   Joseph, Russ ^a  

^a Northwestern University   (United States)

Author keywords

Cache management; Gated VDD; Leakage; Low power; Process variation; Selective cache ways

Indexed keywords

CACHE LEAKAGE MANAGEMENT; GATED-VDD; POWER REDUCTIONS; PROCESS VARIATION; SELECTIVE CACHE WAYS;

COST ACCOUNTING; DOPING (ADDITIVES); LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; QUALITY ASSURANCE;

CACHE MEMORY;

EID: 34247259483     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165636     Document Type: Conference Paper

References (16)

1. A. Agarwal, D. Blaauw, S. Sundareswaran, V. Zolotov, M. Zhou, K. Gala, and R. Panda. Path-based statistical timing analysis considering inter and intra-die correlations. In Proc. of TAU, 2002.
2. D. H. Albonesi. Selective cache ways: On-demand cache resource allocation. In Proc. of the 32nd Annual IEEE/ACM Int. Symp. on Microarchitecture, pages 248-259, Nov. 1999.
3. N. L. Binkert, E. G. Hallnor, and S. K. Reinhardt. Network-oriented full-system simulation using m5. In 6th Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), Feb. 2003.
4. S. Borkar et al. Parameter variations and impact on circuits and microarchitecture. In Proc. of the 40th DAC, 2003.
5. Y. Cao, D. S. T. Sato, M. Orshansky, and C. Hu. New paradigm of predictive mosfet and interconnect modeling for early circuit design. In Proc. of CICC, pages 201-204, 2000. http://www.eas.asu.edu/ptm.
6. H. Chang and S. Sapatnekar. Full-chip analysis of leakage power under process variations - including spatial correlations. In Proceedings of the ACM/IEEE Design Automation Conference, 2005.
7. A. Devgan and S. Nassif. Power variability and its impact on design. In Proceedings of the 18th International Conference on VLSI Design (VLSID-05), 2005.
8. A. Dhodapkar and J. E. Smith. Managing multi-configuration hardware via dynamic working set analysis. In Proc. of 29th Int. Symp. on Computer Architecture (ISCA-29), May 2002.
9. K. Flautner, N. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: Simple techniques for reducing leakage power. In Proceedings of 29th International Symposium on Computer Architecture (ISCA-29), May 2002.
10. P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos. Modeling within-die spatial correlation effects for process-design co-optimization. In Proc. of the 6th Int. Symp. on Quality Electronic Design, 2005.
11. S. Kaxiras, Z. Hu, and M. Martonosi. Cache decay: Exploiting generational behavior to reduce cache leakage power. In Proceedings of the 28th International Symposium on Computer Architecture (ISCA-28), June 2001.
12. C. McNairy and R. Bhatia. Montecito: A dual-core dual-thread itanium processor. IEEE Micro, 25:10-20, Apr. 2005.
13. M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. Vijaykumar. Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In ACM/IEEE ISLPED, 2000.
14. D. B. Rajeev Rao, Ashish Srivastava and D. Sylvester. Statistical analysis of subthreshold leakage current for vlsi circuits. IEEE Trans. on VLSI Systems, 12:131-139, Feb. 2004.
15. Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 2003. http://public.itrs.net/Files/2003ITRS/Home.htm.
16. J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, Fellow, A. P. Chandrakasan, and V. De. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 37:1396-1402, Nov. 2002.