-
1
-
-
29044440093
-
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
-
Dec.
-
D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol.47, no.12, pp. 2320-2325, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Takeuchi, H.4
Asano, K.5
Kuo, C.6
Anderson, E.7
King, T.-J.8
Bokor, J.9
Hu, C.10
-
2
-
-
0036923438
-
FinFET scaling to 10 nm gate length
-
B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in Proc. IEDM Tech. Dig., 2002, pp. 251-254.
-
(2002)
Proc. IEDM Tech. Dig.
, pp. 251-254
-
-
Yu, B.1
Chang, L.2
Ahmed, S.3
Wang, H.4
Bell, S.5
Yang, C.-Y.6
Tabery, C.7
Ho, C.8
Xiang, Q.9
King, T.-J.10
Bokor, J.11
Hu, C.12
Lin, M.-R.13
Kyser, D.14
-
3
-
-
0036684706
-
FinFET design considerations based on 3-D simulation and analytical mdeling
-
Aug.
-
G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E. C.-C. Kan, "FinFET design considerations based on 3-D simulation and analytical mdeling," IEEE Trans. Electron Devices, vol.49, no.8, pp. 1411-1419, Aug. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.8
, pp. 1411-1419
-
-
Pei, G.1
Kedzierski, J.2
Oldiges, P.3
Ieong, M.4
Kan, E.C.-C.5
-
4
-
-
0141974959
-
Impact of three-dimensional transistor on the pattern area reduction of ULSI
-
Oct.
-
S. Watanabe, "Impact of three-dimensional transistor on the pattern area reduction of ULSI," IEEE Trans. Electron Devices, vol.50, no.10, pp. 2073-2080, Oct. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.10
, pp. 2073-2080
-
-
Watanabe, S.1
-
5
-
-
0024170164
-
Characterization of surface mobility on the sidewall of dry-etched trenches
-
C. J. Petti, J. P. Mevittie, and J. D. Plummer, "Characterization of surface mobility on the sidewall of dry-etched trenches," in Proc. IEDM Tech. Dig., 1988, pp. 104-107.
-
(1988)
Proc. IEDM Tech. Dig.
, pp. 104-107
-
-
Petti, C.J.1
Mevittie, J.P.2
Plummer, J.D.3
-
6
-
-
0010259788
-
Study of reactive-ion-etch-induced lattice damage in silicon by Ar, CF4 , NF3 and CHF3 plasmas
-
Aug.
-
I.-W. H. Connick, A. Bhattacharyya, and K. N. Ritz, "Study of reactive-ion-etch-induced lattice damage in silicon by Ar, CF4 , NF3 and CHF3 plasmas," J. Appl. Phys., vol.64, no.4, pp. 2059-2063, Aug. 1988.
-
(1988)
J. Appl. Phys.
, vol.64
, Issue.4
, pp. 2059-2063
-
-
Connick, I.-W.H.1
Bhattacharyya, A.2
Ritz, K.N.3
-
7
-
-
0038614785
-
Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs
-
Mar.
-
J.-S. Lee, Y.-K. Choi, D. Ha, S. Balasubramanian, T.-J. King, and J. Bokor, "Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs," IEEE Electron Device Lett., vol.24, no.3, pp. 186-188, Mar. 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, Issue.3
, pp. 186-188
-
-
Lee, J.-S.1
Choi, Y.-K.2
Ha, D.3
Balasubramanian, S.4
King, T.-J.5
Bokor, J.6
-
8
-
-
0036163060
-
Nanoscale CMOS spacer FinFET for the terabit era
-
DOI 10.1109/55.974801, PII S0741310602001088
-
Y.-K. Choi, T.-J. King, and C. Hu, "Nanoscale CMOS spacer FinFET for the terabit era," IEEE Electron Device Lett., vol.23, no.1, pp. 25-27, Jan. 2002. (Pubitemid 34138833)
-
(2002)
IEEE Electron Device Letters
, vol.23
, Issue.1
, pp. 25-27
-
-
Choi, Y.-K.1
King, T.-J.2
Hu, C.3
-
9
-
-
0008463467
-
-
San Jose, CA. [Online]. Available:
-
International Technology Roadmap for Semiconductors (ITRS). (2007). Semiconductor Industry Association, San Jose, CA. [Online]. Available: http://www.itrs.net/Links/2007ITRS/Home2007.htm
-
(2007)
Semiconductor Industry Association
-
-
-
10
-
-
46149117033
-
Nanofabrication challenges for NEMS
-
Zhuhai, China, Jan.
-
Z. Cui and C. Gu, "Nanofabrication challenges for NEMS," in Proc. 1st IEEE Int. Conf. Nano/Micro Eng. Molecular Syst., Zhuhai, China, Jan. 18-21, 2006, pp. 607-610.
-
(2006)
Proc. 1st IEEE Int. Conf. Nano/Micro Eng. Molecular Syst.
, vol.18-21
, pp. 607-610
-
-
Cui, Z.1
Gu, C.2
-
11
-
-
15544378397
-
Etching submicrometer trenches by using the Bosch process and its application to the fabrication of antireflection structures
-
C. Chang, Y.-F. Wang, Y. Kanamori, J.-J. Shih, Y. Kawai, C.-K. Lee, K.-C. Wu, and M. Esashi, "Etching submicrometer trenches by using the Bosch process and its application to the fabrication of antireflection structures," J. Micromech. Microeng., vol.15, pp. 580-585, 2005.
-
(2005)
J. Micromech. Microeng.
, vol.15
, pp. 580-585
-
-
Chang, C.1
Wang, Y.-F.2
Kanamori, Y.3
Shih, J.-J.4
Kawai, Y.5
Lee, C.-K.6
Wu, K.-C.7
Esashi, M.8
-
12
-
-
34548156061
-
Transition from two-dimensional to three-dimensional quantum confinement in semiconductor quantum wires/quantum dots
-
Q. Zhu, K. F. Karlsson, E. Pelucchi, and E. Kapon, "Transition from two-dimensional to three-dimensional quantum confinement in semiconductor quantum wires/quantum dots," Nano Lett., vol.7, no.8, pp. 2227-2233, 2007.
-
(2007)
Nano Lett.
, vol.7
, Issue.8
, pp. 2227-2233
-
-
Zhu, Q.1
Karlsson, K.F.2
Pelucchi, E.3
Kapon, E.4
-
13
-
-
34548145888
-
Nanometer-scale dielectric imaging of semiconductor nanoparticles: Size-dependent dipolar coupling and contrast reversal
-
Z. Hwan and S.-H. Ahn, "Nanometer-scale dielectric imaging of semiconductor nanoparticles: Size-dependent dipolar coupling and contrast reversal," Nano Lett., vol.7, no.8, pp. 2258-2262, 2007.
-
(2007)
Nano Lett.
, vol.7
, Issue.8
, pp. 2258-2262
-
-
Hwan, Z.1
Ahn, S.-H.2
-
14
-
-
34247178480
-
Fast technique for AFM vertical drift compensation
-
F. Marrinello, P. Bariani, L. de Cjiffre, and E. Savio, "Fast technique for AFM vertical drift compensation," Meas. Sci. Technol., vol.18, pp. 689-696, 2007.
-
(2007)
Meas. Sci. Technol.
, vol.18
, pp. 689-696
-
-
Marrinello, F.1
Bariani, P.2
De Cjiffre, L.3
Savio, E.4
-
15
-
-
0001488964
-
Method for imaging sidewalls by atomic force microscopy
-
May
-
Y. Martin and H. K. Wickramasinghe, "Method for imaging sidewalls by atomic force microscopy," Appl. Phys. Lett., vol.64, no.19, pp. 2498-2500, May 1994.
-
(1994)
Appl. Phys. Lett.
, vol.64
, Issue.19
, pp. 2498-2500
-
-
Martin, Y.1
Wickramasinghe, H.K.2
-
16
-
-
33646400332
-
Atomic force probe for sidewall scanning of nano- and microstructures
-
G. Dai, H. Walff, and F. Pohlenz, "Atomic force probe for sidewall scanning of nano- and microstructures," Appl. Phys. Lett., vol.88, no.17, pp. 171908-1-171908-3, 2006.
-
(2006)
Appl. Phys. Lett.
, vol.88
, Issue.17
, pp. 1719081-1719083
-
-
Dai, G.1
Walff, H.2
Pohlenz, F.3
-
17
-
-
34247195636
-
Nanoscale surface measurements at sidewalls of nano-and micro-structures
-
G. Dai, H. Wolff, T. Weimann, M. Xu, F. Pohlenz, and H.-U. Danzebrink, "Nanoscale surface measurements at sidewalls of nano-and micro-structures," Meas. Sci. Technol., vol.18, pp. 334-340, 2007.
-
(2007)
Meas. Sci. Technol.
, vol.18
, pp. 334-340
-
-
Dai, G.1
Wolff, H.2
Weimann, T.3
Xu, M.4
Pohlenz, F.5
Danzebrink, H.-U.6
-
18
-
-
12744252876
-
Fin sidewall microrough-ness measurement by AFM
-
C. F. H. Gondran, E. Morales, A. Guerry, W. Xiong, C. R. Cleavelin, R. Wise, S. Balasubramanian, and T.-J. King, "Fin sidewall microrough-ness measurement by AFM," Mat. Res. Soc. Symp. Proc., vol.811, pp. 365-370, 2004.
-
(2004)
Mat. Res. Soc. Symp. Proc.
, vol.811
, pp. 365-370
-
-
Gondran, C.F.H.1
Morales, E.2
Guerry, A.3
Xiong, W.4
Cleavelin, C.R.5
Wise, R.6
Balasubramanian, S.7
King, T.-J.8
-
19
-
-
42449130586
-
Characterization of ultrathin SOI film and application to short channel MOSFETs
-
X. Tang, N. Reckinger, G. Larrieu, E. Dubois, D. Flandre, J.-P. Raskin, B. Nysten, A. M. Jonas, and V. Bayot, "Characterization of ultrathin SOI film and application to short channel MOSFETs," Nanotechnology, vol.19, pp. 165703-1-165703-7, 2008.
-
(2008)
Nanotechnology
, vol.19
, pp. 1657031-1657037
-
-
Tang, X.1
Reckinger, N.2
Larrieu, G.3
Dubois, E.4
Flandre, D.5
Raskin, J.-P.6
Nysten, B.7
Jonas, A.M.8
Bayot, V.9
-
20
-
-
0033329310
-
Sub 50-nm FinFET: PMOS
-
X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm FinFET: PMOS," in Proc. IEDM Tech. Dig., 1999, pp. 67-70.
-
(1999)
Proc. IEDM Tech. Dig.
, pp. 67-70
-
-
Huang, X.1
Lee, W.-C.2
Kuo, C.3
Hisamoto, D.4
Chang, L.5
Kedzierski, J.6
Anderson, E.7
Takeuchi, H.8
Choi, Y.-K.9
Asano, K.10
Subramanian, V.11
King, T.-J.12
Bokor, J.13
Hu, C.14
-
22
-
-
13244288703
-
Impacts of probe-tip tilt on scanning probe microscopy
-
Nov./Dec.
-
Z.-H. Kim, S.-H. Ahn, B. Lui, and S. R. Leone, "Impacts of probe-tip tilt on scanning probe microscopy," J. Vac. Sci. Technol. B, vol.22, no.6, pp. 3394-3398, Nov./Dec. 2004.
-
(2004)
J. Vac. Sci. Technol. B
, vol.22
, Issue.6
, pp. 3394-3398
-
-
Kim, Z.-H.1
Ahn, S.-H.2
Lui, B.3
Leone, S.R.4
-
23
-
-
9744238045
-
Oxidation-induced improvement in the sidewall morphology and cross-sectional pro-file of silicon wire waveguides
-
Sep./Oct.
-
J.-I. Takahashi, T. Tsuchizawa, T. Watanabe, and S. I. Itabashi, "Oxidation-induced improvement in the sidewall morphology and cross-sectional pro-file of silicon wire waveguides," J. Vac. Sci. Technol. B, vol.22, no.5, pp. 2522-2525, Sep./Oct. 2004.
-
(2004)
J. Vac. Sci. Technol. B
, vol.22
, Issue.5
, pp. 2522-2525
-
-
Takahashi, J.-I.1
Tsuchizawa, T.2
Watanabe, T.3
Itabashi, S.I.4
-
24
-
-
0034268815
-
Micro-structure transformation of silicon: A newly developed transformation technology for patterning silicon surfaces using the surface migration of silicon atoms by hydrogen annealing
-
T. Sato, K. Mitsutake, I. Mizushima, and Y. Tsunashima, "Micro-structure transformation of silicon: A newly developed transformation technology for patterning silicon surfaces using the surface migration of silicon atoms by hydrogen annealing," Jpn. J. Appl. Phys., vol. 39, no. 9A, pp. 5033-5038, 2000.
-
(2000)
Jpn. J. Appl. Phys.
, vol.39
, Issue.9 A
, pp. 5033-5038
-
-
Sato, T.1
Mitsutake, K.2
Mizushima, I.3
Tsunashima, Y.4
-
25
-
-
0032114638
-
Smoothing of Si trench sidewall surface by chemical dry etching and sacrificial oxidation
-
Jul.
-
A. Yahata, S. Urano, T. Inoue, and T. Shinohe, "Smoothing of Si trench sidewall surface by chemical dry etching and sacrificial oxidation," Jpn. J. Appl. Phys., vol.37, no.7, pp. 3954-3955, Jul. 1998.
-
(1998)
Jpn. J. Appl. Phys.
, vol.37
, Issue.7
, pp. 3954-3955
-
-
Yahata, A.1
Urano, S.2
Inoue, T.3
Shinohe, T.4
-
26
-
-
0347131289
-
Suppression of corner effects in triple-gate MOSFETs
-
Dec.
-
J. G. Fossum, J.-W. Yang, and V. P. Trivedi, "Suppression of corner effects in triple-gate MOSFETs," IEEE Electron Device Lett., vol.24, no.12, pp. 745-747, Dec. 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, Issue.12
, pp. 745-747
-
-
Fossum, J.G.1
Yang, J.-W.2
Trivedi, V.P.3
-
27
-
-
1442360362
-
Multiple-gate SOI MOSFETs
-
J.-P. Colinge, "Multiple-gate SOI MOSFETs," Solid-State Electron., vol.48, pp. 897-905, 2004.
-
(2004)
Solid-State Electron.
, vol.48
, pp. 897-905
-
-
Colinge, J.-P.1
|