A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter

Microelectronics Journal

Volumn 40, Issue 10, 2009, Pages 1441-1448

  Navi, K ^a   Foroutan, V ^b   Rahimi Azghadi, M ^a   Maeen, M ^b   Ebrahimpour, M ^a   Kaveh, M ^b   Kavehei, O ^c  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

^b ISLAMIC AZAD UNIVERSITY   (Iran)

^c UNIVERSITY OF ADELAIDE   (Australia)

Author keywords

Inverter based full adder design; Low power CMOS design; Low power Full adder; Transmission gate

Indexed keywords

90NM CMOS; ARITHMETIC CIRCUIT; CMOS INVERTERS; DESIGN APPROACHES; FULL ADDERS; FULL-SWING; IC PACKAGE; INVERTER-BASED FULL-ADDER DESIGN; LAYOUT IMPLEMENTATIONS; LOGICAL GATES; LOW POWER; LOW-POWER CMOS DESIGN; LOW-POWER FULL-ADDER; NOT GATE; POWER CONSUMPTION; REALISTIC APPLICATIONS; SIMULATION STRUCTURE; SYNOPSYS; TRANSMISSION GATE; UNIVERSAL GATES; XOR GATES;

BANDPASS FILTERS; CELL MEMBRANES; DESIGN; ENERGY EFFICIENCY;

ADDERS;

EID: 70049097174     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2009.06.005     Document Type: Article

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