A Novel Multiplexer-Based Low-Power Full Adder

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 51, Issue 7, 2004, Pages 345-348

  Jiang, Yingtao ^a   Al Sheraidah, Abdulkarim ^b   Wang, Yuke ^b   Sha, Edwin ^b   Chung, Jin Gyun ^c  

^a University of Nevada Las Vegas   (United States)

^b The University of Texas at Dallas   (United States)

^c Chonbuk National University   (South Korea)

Author keywords

Full adder; low power; multiplexer; very large scale integrated (VLSI) circuit

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MULTIPLEXING EQUIPMENT; POWER INTEGRATED CIRCUITS; SHORT CIRCUIT CURRENTS; VLSI CIRCUITS;

FULL ADDER; LOW POWER MULTIPLEXER; MULTIPLEXER BASED ADDER; POWER CONSUMPTION;

ADDERS;

EID: 3543004108     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2004.831429     Document Type: Article

References (9)

1. R. Shalem, E. John, and L.K. John, “A novel low-power energy recovery full adder cell,” in Proc. Great Lakes Symp. VLSI, Feb. 1999, pp. 380-383.
2. A.P. Chandrakasan, S. Sheng, and R.W. Broderson, “Low-power CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, pp. 473-483, Apr. 1992.
3. R. Pedram and M. Pedram, Low Power Design Methodologies. Norwell, MA: Kluwer, 1996.
4. H.T. Bui, A.K. Al-Sheraidah, and Y. Wang, “Design and analysis of 10-transistor full adders using novel XOR-XNOR gates,” in Proc. Int. Conf. Signal Processing 2000 (Wold Computer Congress), Beijing, China, Aug. 2000.
5. J. Wang, S. Fang, and W. Feng, “Newefficient designs for XOR and XNOR functions on the transistor level,” IEEE J. Solid-State Circuits, vol. 29, pp. 780-786, July 1994.
6. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective. Reading, MA: Addison-Wesley, 1993.
7. R. Zimmermannn and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE J. Solid-State Circuits, vol. 32, pp. 1079-1090, July 1997.
8. Y. Jiang, Y. Wang, and J. Wu, “Comprehensive Power Evaluation of Full Adders,” Florida Atlantic Univ., Boca Raton, Tech. Rep., 2000.
9. Meta-Software, HSPICE User's Manual Version H9002, 1992.