Low-voltage low-power CMOS full adder

IEE Proceedings: Circuits, Devices and Systems

Volumn 148, Issue 1, 2001, Pages 19-24

  Radhakrishnan, D ^a  

^a STATE UNIVERSITY OF NEW YORK   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CONSUMER ELECTRONICS; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); LOGIC DEVICES; MOSFET DEVICES; PORTABLE EQUIPMENT;

FULL ADDERS;

ADDERS;

EID: 0035247455     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20010170     Document Type: Article

References (22)

1. Designing low power CMOS
2. A 3.8-ns CMOS 16 × 16-b multiplier using complementary pass-transistor logic
3. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
4. Formal design procedures for pass transistor switching circuits
5. Design of CMOS circuits
6. Analysis and synthesis of combinational pass transistor circuits
7. New efficient designs for XOR and XNOR functions on the transistor level
8. Formal design procedures for low-power CMOS full adder cells
9. New low-voltage circuits for XOR and XNOR
10. A structured approach for designing low power adders
11. A new full adder cell for low-power applications
12. A new design of the cmos full adder
13. A low-power true single phase clocked (TSPC) full-adder
14. A 2.6-ns 64-b fast and small CMOS adder
15. Power consumption and performance of low-voltage bit-serial adders
16. High performance low power low voltage adder
17. Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers
18. A new cell for low power adders
19. A new low-voltage full adder circuit