Two new low-power Full Adders based on majority-not gates

Microelectronics Journal

Volumn 40, Issue 1, 2009, Pages 126-130

  Navi, Keivan ^a   Moaiyeri, Mohammad Hossein ^a   Mirzaee, Reza Faghih ^a   Hashemipour, Omid ^a   Nezhad, Babak Mazloom ^a  

^a SHAHID BEHESHTI UNIVERSITY   (Iran)

Author keywords

Full Adder cell; Low power; Majority not gate; Power delay product

Indexed keywords

BRIDGE CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC POWER UTILIZATION;

CMOS INVERTERS; CMOS TECHNOLOGIES; FULL ADDER CELL; INPUT CAPACITORS; LOW-POWER; MAJORITY-NOT GATE; POWER CONSUMPTIONS; POWER-DELAY PRODUCT; SIMULATION RESULTS; SUPPLY VOLTAGES;

ADDERS;

EID: 57849150789     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2008.08.020     Document Type: Article

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