Novel low power energy recovery full adder cell

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1999, Pages 380-383

  Shalem, R ^a   John, E ^a   John, L K ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; EFFICIENCY; ELECTRIC CURRENTS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; TRANSISTORS;

DUAL VALUE LOGIC ADDER; POWER CONSUMPTION; PROPAGATION DELAY; STATIC ENERGY FULL ADDER; TRANSMISSION FUNCTION ADDER;

ADDERS;

EID: 0033312440     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)